DATE 2003 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Aarts, E.
IC Design Challenges for Ambient Intelligence [p. 2]
Abadir, M.
Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step [p. 328]
Abid, M.
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs [p. 674]
Achouri, N.
Optimal Reconfiguration Functions for Column or Data-Bit Built-In Self-Repair [p. 590]
Agarwal, A.
Statistical Timing Analysis Using Bounds [p. 62]
Agarwal, A.
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology [p. 778]
Ahmed, N.
Extending JTAG for Testing Signal Integrity in SoCs [p. 218]
Akgul, B.
PARLAK: Parametrized Lock Cache Generator [p. 1138]
Alarcón, E.
Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters [p. 636]
Al-Ars, Z.
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation [p. 484]
Albiol, M.
Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters [p. 636]
Al-Hashimi, B.
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems [p. 90]
Al-Hashimi, B.
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric [p. 596]
Al-Hashimi, B.
Test Data Compression: The System Integrator's Perspective [p. 726]
Al-Hashimi, B.
A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities [p. 960]
Alves, G.
Run-Time Management of Logic Resources on Reconfigurable Systems [p. 974]
Andriahantenaina, A.
Micro-Network for SoC: Implementation of a 32-Port SPIN Network [p. 1128]
Anido, M.
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures [p. 36]
Aragonès, X.
Modeling and Evaluation of Substrate Noise Induced by Interconnects [p. 524]

B

Bacivarov, I.
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer [p. 550]
Bagherzadeh, N.
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures [p. 36]
Bagherzadeh, N.
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver [p. 468]
Balarin, F.
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula [p. 1174]
Bampi, S.
LIT -- An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks [p. 1106]
Banerjee, S.
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation [p. 784]
Barua, R.
Dynamic Functional Unit Assignment for Low Power [p. 1052]
Bauer, M.
Platform Based Testbench Generation [p. 1038]
Baumgarte, V.
An Industrial/Academic Configurable System-On-Chip Project (CSoC): Coarse-Grain XPP-/Leon-Based Architecture Integration [p. 1120]
Bazargan, K.
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration [p. 1104]
Becker, B.
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST [p. 1184]
Becker, J.
An Industrial/Academic Configurable System-On-Chip Project (CSoC): Coarse-Grain XPP-/Leon-Based Architecture Integration [p. 1120]
Ben Amor, N.
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs [p. 674]
Benini, L.
Packetized On-Chip Interconnect Communication Analysis for MPSoC [p. 344]
Benini, L.
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms [p. 516]
Benini, L.
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems [p. 706]
Bergamaschi, R.
Modeling and Integration of Peripheral Devices in Embedded Systems [p. 136]
Bernardi, P.
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories [p. 720]
Bertozzi, D.
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems [p. 706]
Bhattacharya, B.
Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform [p. 662]
Bhunia, S.
Synthesis of Application-Specific Highly Efficient Multi-Mode Systems for Low-Power Applications [p. 96]
Blaauw, D.
Statistical Timing Analysis Using Bounds [p. 62]
Blodget, B.
A Lightweight Approach for Embedded Reconfiguration of FPGAs [p. 399]
Bobda, C.
A Fully Self-Timed Bit-Serial Pipeline-Architecture for Embedded Systems [p. 1130]
Borgatti, M.
Different Approaches to Add Reconfigurability in a SoC Architecture [p. 398]
Bouchhima, A.
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer [p. 550]
Boutobza, S.
Optimal Reconfiguration Functions for Column or Data-Bit Built-In Self-Repair [p. 590]
Brandolese, C.
Library Functions Timing Characterization for Source-Level Analysis [p. 1132]
Braun, G.
Processor/Memory Co-Exploration on Multiple Abstraction Levels [p. 966]
Braun, J.
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation [p. 484]
Brayton, R.
Reducing Multi-Valued Algebraic Operations to Binary [p. 752]
Brayton, R.
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations [p. 1154]
Brockmeyer, E.
Layer Assignment Techniques for Low Energy in Multi-Layered Memory Organisations [p. 1070]
Brockmeyer, E.
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor [p. 1144]
Brooks, R.
Masking the Energy Behavior of DES Encryption [p. 84]
Bruni, D.
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms [p. 516]
Bryant, R.
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis [p. 816]
Burbidge, M.
Techniques for Automatic on Chip Closed Loop Transfer Function Monitoring for Embedded Charge Pump Phase Locked Loops [p. 496]
Bystrov, A.
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design [p. 926]
Bystrov, A.
STG Optimisation in the Direct Mapping of Asynchronous Circuits [p. 932]

C

Cabodi, G.
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals [p. 898]
Calazans, N.
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs [p. 1122]
Cambonie, J.
Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform [p. 662]
Canavero, F.
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices [p. 536]
Candaele, B.
Embedded Software in Digital AM-FM Chipset [p. 340]
Cardoso, J.
From C Programs to the Configure-Execute Model [p. 576]
Cassidy, A.
Layered, Multi-Threaded, High-Level Performance Design [p. 954]
Castro-López, R.
Behavioural Modelling and Simulation of Delta-Sigma Modulators Using Hardware Description Languages [p. 168]
Catthoor, F.
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms [p. 516]
Catthoor, F.
Layer Assignment Techniques for Low Energy in Multi-Layered Memory Organisations [p. 1070]
Catthoor, F.
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor [p. 1144]
Chakraborty, S.
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs [p. 190]
Chakraborty, K.
EBIST: A Novel Test Generator with Built-In Fault Detection Capability [p. 224]
Chakrabarty, K.
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-On-Chip Fault Diagnosis [p. 230]
Chakrabarty, K.
Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems [p. 918]
Chakrabarty, K.
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization [p. [p. 1188]
Chandra, A.
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization [p. [p. 1188]
Chandra, V.
Heterogeneous Programmable Logic Block Architectures [p. 1118]
Chang, A.
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer [p. 1134]
Chang, Y.
On Modeling Cross-Talk Faults [p. 490]
Chen, C.
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method [p. 1020]
Chen, G.
Data Space Oriented Scheduling in Embedded Systems [p. 416]
Chen, H.
Global Wire Bus Configuration with Minimum Delay Uncertainty [p. 50]
Chen, X.
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula [p. 1174]
Chen, Y.
Area Fill Generation with Inherent Data Volume Reduction [p. 868]
Cheng, K.
Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step [p. 328]
Cheng, K.
A Circuit SAT Solver with Signal Correlation Guided Learning [p. 892]
Cheng, W.
Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface [p. 694]
Cheung, N.
Rapid Configuration and Instruction Selection for an ASIP: A Case Study [p. 802]
Cheung, P.
Mesh Partitioning Approach to Energy Efficient Data Layout [p. 1076]
Chiou, L.
Synthesis of Application-Specific Highly Efficient Multi-Mode Systems for Low-Power Applications [p. 96]
Choi, S.
A New Crosstalk Noise Model for DOMINO Logic Circuits [p. 1112]
Choi, W.
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration [p. 1104]
Choo, H.
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters [p. 700]
Choudhary, A.
An Integrated Approach for Improving Cache Behavior [p. 796]
Chu, C.
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees [p. 856]
Ciesielski, M.
Fast Computation of Data Correlation Using BDDs [p. 122]
Coene, P.
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-On-Chip [p. 986]
Corno, F.
Fully Automatic Test Program Generation for Microprocessor Cores [p. 1006]
Corporaal, H.
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms [p. 516]
Corporaal, H.
Layer Assignment Techniques for Low Energy in Multi-Layered Memory Organisations [p. 1070]
Corsi, F.
An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme [p. 1178]
Crudo, F.
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors [p. 24]
Cumani, G.
Fully Automatic Test Program Generation for Microprocessor Cores [p. 1006]
Cuomo, A.
Semiconductor Challenges [p. 8]

D

Daems, W.
Generalized Posynomial Performance Modeling [p. 250]
Dales, M.
Managing a Reconfigurable Processor in a General Purpose Workstation Environment [p. 980]
Dasgupta, P.
A Novel Metric for Interconnect Architecture Performance [p. 448]
de Kock, E.
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs [p. 656]
De La Luz, V.
Generalized Data Transformations for Enhancing Cache Behavior [p. 906]
De Man, H.
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling [p. 296]
De Man, H.
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver [p. 642]
De Micheli, G.
Packetized On-Chip Interconnect Communication Analysis for MPSoC [p. 344]
De Smedt, B.
Holmes: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits [p. 256]
De, V.
Compiler Support for Reducing Leakage Energy Consumption [p. 1146]
Deb, A.
Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology [p. 1100]
Deconinck, G.
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor [p. 1144]
Deprettere, E.
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs [p. 656]
Dielissen, J.
Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip [p. 350]
Diguet, J.
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs [p. 674]
Ding, L.
Modeling Noise Transfer Characteristic of Dynamic Logic Gates [p. 1114]
Doboli, A.
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering [p. 1098]
Doboli, S.
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering [p. 1098]
Dobrovolný, P.
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits [p. 624]
Donnay, S.
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits [p. 624]
Donnay, S.
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver [p. 642]
Doucet, F.
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated [p. 382]
Doucet, F.
Polychrony for Refinement-Based Design [p. 1172]
Drechsler, R.
Combination of Lower Bounds in Exact BDD Minimization [p. 758]
Drineas, P.
Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees [p. 1164]
Du, H.
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures [p. 36]
Dumitras, T.
On-Chip Stochastic Communication [p. 790]
Dutt, N.
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs [p. 270]
Dutt, N.
On-Chip Stack Based Memory Organization for Low Power Embedded Architectures [p. 1082]

E

Ebadi, Z.
Time Domain Multiplexed TAM: Implementation and Comparison [p. 732]
Ebendt, R.
Combination of Lower Bounds in Exact BDD Minimization [p. 758]
Eberle, W.
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver [p. 642]
Ecker, W.
Platform Based Testbench Generation [p. 1038]
Eckl, K.
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information [p. 770]
Eeckelaert, T.
Generalized Posynomial Performance Modeling [p. 250]
Eikerling, H.
Dynamic Tool Integration in Heterogeneous Computer Networks [p. 946]
Einwich, K.
SystemC-AMS Requirements, Design Objectives and Rationale [p. 388]
Eles, P.
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems [p. 90]
Eles, P.
Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems [p. 184]
Eles, P.
A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities [p. 960]
Ernst, R.
Safe Automotive Software Development [p. 616]

F

Falk, H.
Control Flow Driven Splitting of Loop Nests at the Source Code Level [p. 410]
Fazel, K.
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs [p. 1096]
Fei, Y.
Energy Estimation for Extensible Processors [p. 682]
Feldmann, R.
SAT-Based Techniques in System Synthesis [p. 1168]
Fernandes, J.
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST [p. 994]
Fernández, F.
Behavioural Modelling and Simulation of Delta-Sigma Modulators Using Hardware Description Languages [p. 168]
Fernández, M.
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures [p. 36]
Ferreira, J.
Run-Time Management of Logic Resources on Reconfigurable Systems [p. 974]
Fornaciari, W.
A First Step Towards HW/SW Partitioning of UML Specifications [p. 668]
Fornaciari, W.
Library Functions Timing Characterization for Source-Level Analysis [p. 1132]
Freitas, A.
Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation [p. 764]
Friedman, E.
Reduced Delay Uncertainty in High Performance Clock Distribution Networks [p. 68]
Fujiwara, H.
A Method of Test Generation for Path Delay Faults Using Stuck-At Fault Test Generation Algorithms [p. 310]

G

Gajski, D.
RTOS Modeling for System Level Design [p. 130]
Gericota, M.
Run-Time Management of Logic Resources on Reconfigurable Systems [p. 974]
Gerling, J.
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects [p. 1110]
Gerstlauer, A.
RTOS Modeling for System Level Design [p. 130]
Ghez, C.
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor [p. 1144]
Ghosh, A.
Analytical Design Space Exploration of Caches for Embedded Systems [p. 650]
Gielen, G.
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver [p. 642]
Gielen, G.
Figure of Merit Based Selection of A/D Converters [p. 1190]
Gielen, G.
A Model of Computation for Continuous-Time Delta-Sigma Modulators [p. 162]
Gielen, G.
Generalized Posynomial Performance Modeling [p. 250]
Gielen, G.
Holmes: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits [p. 256]
Gielen, G.
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors [p. 238]
Gilbert, F.
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors [p. 356]
Girardi, A.
LIT -- An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks [p. 1106]
Givargis, T.
Analytical Design Space Exploration of Caches for Embedded Systems [p. 650]
Gizopoulos, D.
Low-Cost Software-Based Self-Testing of RISC Processor Cores [p. 714]
Glesner, M.
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues [p. 940]
Goel, A.
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis [p. 816]
Goel, K.
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization [p. 738]
Goldberg, E.
Verification of Proofs of Unsatisfiability for CNF Formulas [p. 886]
Gomez, J.
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms [p. 516]
Gonciari, P.
Test Data Compression: The System Integrator's Perspective [p. 726]
González, J.
Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters [p. 636]
Goossens, K.
Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip [p. 350]
Gothoskar, G.
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering [p. 1098]
Gourary, M.
Approximation Approach for Timing Jitter Characterization in Circuit Simulators [p. 156]
Gourary, M.
A New Simulation Technique for Periodic Small-Signal Analysis [p. 244]
Greiner, A.
Micro-Network for SoC: Implementation of a 32-Port SPIN Network [p. 1128]
Grimm, C.
SystemC-AMS Requirements, Design Objectives and Rationale [p. 388]
Grimm, C.
Refinement of Mixed-Signal Systems with SystemC [p. 1170]
Grivet-Talocia, S.
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices [p. 536]
Gullapalli, K.
Approximation Approach for Timing Jitter Characterization in Circuit Simulators [p. 156]
Günther, W.
Combination of Lower Bounds in Exact BDD Minimization [p. 758]
Guo, Y.
Mapping Applications to an FPFA Tile [p. 1124]
Gupta, B.
Different Approaches to Add Reconfigurability in a SoC Architecture [p. 398]
Gupta, R.
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs [p. 270]
Gupta, R.
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated [p. 382]
Gupta, R.
Polychrony for Refinement-Based Design [p. 1172]
Gupta, S.
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs [p. 270]

H

Haga, S.
Dynamic Functional Unit Assignment for Low Power [p. 1052]
Harris, I.
Fast Computation of Data Correlation Using BDDs [p. 122]
Haubelt, C.
SAT-Based Techniques in System Synthesis [p. 1168]
Haug, G.
Instruction Set Emulation for Rapid Prototyping of SoCs [p. 562]
Henftling, R.
Platform Based Testbench Generation [p. 1038]
Henkel, J.
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses [p. 542]
Henkel, J.
Rapid Configuration and Instruction Selection for an ASIP: A Case Study [p. 802]
Hermida, R.
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures [p. 36]
Hermida, R.
High-Level Allocation to Minimize Internal Hardware Wastage [p. 264]
Herrera, F.
Systematic Embedded Software Generation from SystemC [p. 142]
Hettiaratchi, S.
Mesh Partitioning Approach to Energy Efficient Data Layout [p. 1076]
Heupke, W.
Refinement of Mixed-Signal Systems with SystemC [p. 1170]
Hsiao, M.
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification [p. 316]
Hsiao, M.
Efficient Preimage Computation Using a Novel Success-Driven ATPG [p. 822]
Hsieh, H.
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula [p. 1174]
Hu, J.
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures [p. 688]
Huang, L.
Global Wire Bus Configuration with Minimum Delay Uncertainty [p. 50]
Huang, R.
A Circuit SAT Solver with Signal Correlation Guided Learning [p. 892]
Huang, S.
Decomposition of Extended Finite State Machine for Low Power Design [p. 1152]
Hwang, T.
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs [p. 1102]
Hwang, T.
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer [p. 1134]
Hwang, T.
Decomposition of Extended Finite State Machine for Low Power Design [p. 1152]

I

Ichihara, H.
Test Generation for Acyclic Sequential Circuits with Single Stuck-At Fault Combinational ATPG [p. 1180]
Indrusiak, L.
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues [p. 940]
Inoue, T.
Test Generation for Acyclic Sequential Circuits with Single Stuck-At Fault Combinational ATPG [p. 1180]
Irwin, M.
Masking the Energy Behavior of DES Encryption [p. 84]
Irwin, M.
Compiler Support for Reducing Leakage Energy Consumption [p. 1146]
Ivanov, A.
Time Domain Multiplexed TAM: Implementation and Comparison [p. 732]
Iyengar, V.
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization [p. [p. 1188]

J

Jacome, M.
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling [p. 422]
Jantsch, A.
Development and Application of Design Transformations in ForSyDe [p. 364]
Jantsch, A.
Load Distribution with the Proximity Congestion Awareness in a Network On Chip [p. 1126]
Jantsch, A.
Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology [p. 1100]
Jentschel, H.
RF-BIST: Loopback Spectral Signature Analysis [p. 478]
Jerraya, A.
Introduction to Hardware Abstraction Layers for SoC [p. 336]
Jerraya, A.
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer [p. 550]
Jha, N.
Energy Estimation for Extensible Processors [p. 682]
Jha, N.
Software Architectural Transformations: A New Approach to Low Energy Embedded Software [p. 1046]
Jha, N.
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems [p. 1150]
Jiang, J.
Reducing Multi-Valued Algebraic Operations to Binary [p. 752]
Johannes, F.
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information [p. 770]
Jongeneel, D.
Time Budgeting in a Wireplanning Context [p. 436]

K

Kadayif, I.
An Integrated Approach for Improving Cache Behavior [p. 796]
Kadayif, I.
Generalized Data Transformations for Enhancing Cache Behavior [p. 906]
Kahng, A.
A Novel Metric for Interconnect Architecture Performance [p. 448]
Kahng, A.
Area Fill Generation with Inherent Data Volume Reduction [p. 868]
Kamalizad, A.
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver [p. 468]
Kandemir, M.
Data Space Oriented Scheduling in Embedded Systems [p. 416]
Kandemir, M.
Runtime Code Parallelization for On-Chip Multiprocessors [p. 510]
Kandemir, M.
An Integrated Approach for Improving Cache Behavior [p. 796]
Kandemir, M.
Generalized Data Transformations for Enhancing Cache Behavior [p. 906]
Kandemir, M.
Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy [p. 1058]
Kandemir, M.
Compiler Support for Reducing Leakage Energy Consumption [p. 1146]
Kandemir, M.
Masking the Energy Behavior of DES Encryption [p. 84]
Kapur, R.
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture [p. 110]
Karakoy, M.
Runtime Code Parallelization for On-Chip Multiprocessors [p. 510]
Karri, S.
Using Formal Techniques to Debug the AMBA System-On-Chip Bus Protocol [p. 828]
Kazmierski, T.
A Secure Web-Based Framework for Electronic System Level Design [p. 1140]
Kebschull, U.
Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems [p. 302]
Kennedy, M.
Linear Model-Based Error Identification and Calibration for Data Converters [p. 630]
Khomenko, V.
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design [p. 926]
Kim, E.
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units [p. 276]
Kim, S.
Masking the Energy Behavior of DES Encryption [p. 84]
Kin, J.
Multithreaded Synchronous Data Flow Simulation [p. 1094]
Knieser, M.
A Technique for High Ratio LZW Compression [p. 116]
Koh, C.
Interconnect Planning with Local Area Constrained Retiming [p. 442]
Kolcu, I.
Data Space Oriented Scheduling in Embedded Systems [p. 416]
Kolcu, I.
Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy [p. 1058]
Kondratyev, A.
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling [p. 428]
Koohi, A.
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver [p. 468]
Koorapaty, A.
Heterogeneous Programmable Logic Block Architectures [p. 1118]
Kopetz, H.
Safe Automotive Software Development [p. 616]
Kranitis, N.
Low-Cost Software-Based Self-Testing of RISC Processor Cores [p. 714]
Kraus, O.
XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines [p. 1092]
Krol, T.
Mapping Applications to an FPFA Tile [p. 1124]
Krstic, A.
Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step [p. 328]
Kuacharoen, P.
Software Streaming via Block Streaming [p. 912]
Kuenzli, S.
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs [p. 190]
Kundu, S.
On Modeling Cross-Talk Faults [p. 490]
Kundu, S.
On the Characterization of Hard-To-Detect Bridging Faults [p. 1012]
Kunz, W.
Using RTL Statespace Information and State Encoding for Induction Based Property Checking [p. 1156]
Kuo, W.
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs [p. 1102]
Kuo, W.
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer [p. 1134]

L

La Rosa, A.
Hardware/Software Design Space Exploration for a Reconfigurable Processor [p. 570]
Lange, S.
Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems [p. 302]
Lauwereins, R.
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling [p. 296]
Lauwereins, R.
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-On-Chip [p. 986]
Lavagno, L.
Hardware/Software Design Space Exploration for a Reconfigurable Processor [p. 570]
Lavagno, L.
Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform [p. 662]
Le Guernic, P.
Polychrony for Refinement-Based Design [p. 1172]
Le Moullec, Y.
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs [p. 674]
Lee, D.
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units [p. 276]
Lee, J.
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units [p. 276]
Lee, M.
Decomposition of Extended Finite State Machine for Low Power Design [p. 1152]
Lee, Y.
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method [p. 1020]
Lehmann, T.
A Fully Self-Timed Bit-Serial Pipeline-Architecture for Embedded Systems [p. 1130]
Lekatsas, H.
Profile-Driven Selective Code Compression [p. 462]
Lekatsas, H.
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses [p. 542]
Leupers, R.
Processor/Memory Co-Exploration on Multiple Abstraction Levels [p. 966]
Li, P.
Noise Macromodel for Radio Frequency Integrated Circuits [p. 150]
Li, X.
Noise Macromodel for Radio Frequency Integrated Circuits [p. 150]
Li, Z.
Symbolic Analysis of Nonlinear Analog Circuits [p. 1108]
Liou, J.
Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step [p. 328]
Liu, C.
EBIST: A Novel Test Generator with Built-In Fault Detection Capability [p. 224]
Liu, C.
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-On-Chip Fault Diagnosis [p. 230]
Lo, J.
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs [p. 1102]
Logothetis, G.
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration [p. 196]
Lomeña, A.
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling [p. 428]
López-Vallejo, M.
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling [p. 428]
Lu, F.
A Circuit SAT Solver with Signal Correlation Guided Learning [p. 892]
Lu, R.
Interconnect Planning with Local Area Constrained Retiming [p. 442]
Lu, Z.
Development and Application of Design Transformations in ForSyDe [p. 364]
Lubitz, F.
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues [p. 940]
Luo, J.
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems [p. 1150]
Lupea, D.
RF-BIST: Loopback Spectral Signature Analysis [p. 478]
Lv, T.
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses [p. 542]
Lysaght, P.
A Lightweight Approach for Embedded Reconfiguration of FPGAs [p. 399]

M

Macii, A.
Improving the Efficiency of Memory Partitioning by Address Clustering [p. 18]
Macii, A.
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors [p. 24]
Macii, E.
Improving the Efficiency of Memory Partitioning by Address Clustering [p. 18]
Macii, E.
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors [p. 24]
Madalinski, A.
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design [p. 926]
Madden, P.
Crosstalk Reduction in Area Routing [p. 862]
Madisetti, V.
Software Streaming via Block Streaming [p. 912]
Madsen, J.
Power Constrained High-Level Synthesis of Battery Powered Systems [p. 1136]
Maio, I.
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices [p. 536]
Makris, Y.
Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees [p. 1164]
Malik, S.
Modeling and Integration of Peripheral Devices in Embedded Systems [p. 136]
Malik, S.
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation [p. 556]
Malik, S.
Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and other Applications [p. 880]
Mamidipaka, M.
On-Chip Stack Based Memory Organization for Low Power Embedded Architectures [p. 1082]
Mansour, M.
Model-Order Reduction Based on PRONY's Method [p. 530]
Manthe, A.
Symbolic Analysis of Nonlinear Analog Circuits [p. 1108]
Marchal, P.
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms [p. 516]
Marculescu, D.
Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications [p. 504]
Marculescu, D.
Dynamic Functional Unit Assignment for Low Power [p. 1052]
Marculescu, R.
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures [p. 688]
Marculescu, R.
On-Chip Stochastic Communication [p. 790]
Marek-Sadowska, M.
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique [p. 850]
Marinissen, E.
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization [p. 738]
Martens, E.
A Model of Computation for Continuous-Time Delta-Sigma Modulators [p. 162]
Martorell, F.
Modeling and Evaluation of Substrate Noise Induced by Interconnects [p. 524]
Marwedel, P.
Control Flow Driven Splitting of Loop Nests at the Source Code Level [p. 410]
Marzocca, C.
An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme [p. 1178]
Matarrese, G.
An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme [p. 1178]
Mateo, D.
Modeling and Evaluation of Substrate Noise Induced by Interconnects [p. 524]
Mayaram, K.
Symbolic Analysis of Nonlinear Analog Circuits [p. 1108]
Mazumder, P.
Modeling Noise Transfer Characteristic of Dynamic Logic Gates [p. 1114]
Mazzeo, A.
FPGA-Based Implementation of a Serial RSA Processor [p. 582]
Mazzocca, N.
FPGA-Based Implementation of a Serial RSA Processor [p. 582]
McIntyre, R.
A Technique for High Ratio LZW Compression [p. 116]
McMillan, S.
A Lightweight Approach for Embedded Reconfiguration of FPGAs [p. 399]
Medeiro, F.
Behavioural Modelling and Simulation of Delta-Sigma Modulators Using Hardware Description Languages [p. 168]
Mehrotra, A.
Model-Order Reduction Based on PRONY's Method [p. 530]
Mei, B.
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling [p. 296]
Meise, C.
Refinement of Mixed-Signal Systems with SystemC [p. 1170]
Memik, G.
An Integrated Approach for Improving Cache Behavior [p. 796]
Mendías, J.
High-Level Allocation to Minimize Internal Hardware Wastage [p. 264]
Merel, D.
Embedded Software in Digital AM-FM Chipset [p. 340]
Mesquita, D.
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs [p. 1122]
Metra, C.
High Speed and Highly Testable Parallel Two -Rail Code Checker [p. 608]
Meyr, H.
Processor/Memory Co-Exploration on Multiple Abstraction Levels [p. 966]
Micheli, P.
A First Step Towards HW/SW Partitioning of UML Specifications [p. 668]
Mignolet, J.
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-On-Chip [p. 986]
Millberg, M.
Load Distribution with the Proximity Congestion Awareness in a Network On Chip [p. 1126]
Miranda, M.
Layer Assignment Techniques for Low Energy in Multi-Layered Memory Organisations [p. 1070]
Miranda, M.
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor [p. 1144]
Mishchenko, A.
Reducing Multi-Valued Algebraic Operations to Binary [p. 752]
Mitra, T.
Using Formal Techniques to Debug the AMBA System-On-Chip Bus Protocol [p. 828]
Molina, M.
High-Level Allocation to Minimize Internal Hardware Wastage [p. 264]
Möller, L.
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs [p. 1122]
Mong, W.
Specification of Non-Functional Intellectual Property Components [p. 456]
Monien, B.
SAT-Based Techniques in System Synthesis [p. 1168]
Mooney III, V.
Automated Bus Generation for Multiprocessor SoC Design [p. 282]
Mooney III, V.
Hardware/Software Partitioning of Operating Systems [p. 338]
Mooney, V.
Software Streaming via Block Streaming [p. 912]
Mooney, V.
PARLAK: Parametrized Lock Cache Generator [p. 1138]
Moraes, F.
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs [p. 1122]
Mrozynski, G.
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects [p. 1110]
Muddu, S.
A Novel Metric for Interconnect Architecture Performance [p. 448]
Mueller, W.
Dynamic Tool Integration in Heterogeneous Computer Networks [p. 946]
Muhammad, K.
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters [p. 700]
Mulvaney, B.
Approximation Approach for Timing Jitter Characterization in Circuit Simulators [p. 156]
Mulvaney, J.
A New Simulation Technique for Periodic Small-Signal Analysis [p. 244]

N

Nakamura, H.
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units [p. 276]
Nandy, S.
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation [p. 784]
Nanya, T.
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units [p. 276]
Nicolaescu, D.
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors [p. 1064]
Nicolaidis, M.
Optimal Reconfiguration Functions for Column or Data-Bit Built-In Self-Repair [p. 590]
Nicolau, A.
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs [p. 270]
Nicolau, A.
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors [p. 1064]
Nicolici, N.
Test Data Compression: The System Integrator's Perspective [p. 726]
Nicolici, N.
Delay Fault Testing of Core-Based Systems-On-A-Chip [p. 744]
Nielsen, S.
Power Constrained High-Level Synthesis of Battery Powered Systems [p. 1136]
Nilsson, E.
Load Distribution with the Proximity Congestion Awareness in a Network On Chip [p. 1126]
Nocco, S.
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals [p. 898]
Nohl, A.
Processor/Memory Co-Exploration on Multiple Abstraction Levels [p. 966]
Nollet, V.
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-On-Chip [p. 986]
Nourani, M.
Extending JTAG for Testing Signal Integrity in SoCs [p. 218]
Novák, O.
Comparison of Test Pattern Decompression Techniques [p. 1182]
Novikov, Y.
Local Search for Boolean Relations on the Basis of Unit Propagation [p. 810]
Novikov, Y.
Verification of Proofs of Unsatisfiability for CNF Formulas [p. 886]
Nummer, M.
DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers [p. 212]

O

Öberg, J.
Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology [p. 1100]
Öberg, J.
Load Distribution with the Proximity Congestion Awareness in a Network On Chip [p. 1126]
Oh, N.
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture [p. 110]
Ohtake, S.
A Method of Test Generation for Path Delay Faults Using Stuck-At Fault Test Generation Algorithms [p. 310]
Ohtani, K.
A Method of Test Generation for Path Delay Faults Using Stuck-At Fault Test Generation Algorithms [p. 310]
Oikonomakos, P.
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric [p. 596]
Oliveira, A.
Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation [p. 764]
Omaña, M.
High Speed and Highly Testable Parallel Two -Rail Code Checker [p. 608]
Op de Beeck, P.
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor [p. 1144]
Orailoglu, A.
Power Efficiency through Application-Specific Instruction Memory Transformations [p. 30]
Orailoglu, A.
Virtual Compression through Test Vector Stitching for Scan Based Design [p. 104]
Otten, R.
Time Budgeting in a Wireplanning Context [p. 436]

P

Padeffke, M.
XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines [p. 1092]
Padmanaban, S.
Non-Enumerative Path Delay Fault Diagnosis [p. 322]
Palma, J.
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs [p. 1122]
Pan, C.
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver [p. 468]
Papachristou, C.
A Technique for High Ratio LZW Compression [p. 116]
Papaefthymiou, M.
Reduced Delay Uncertainty in High Performance Clock Distribution Networks [p. 68]
Parameswaran, S.
Rapid Configuration and Instruction Selection for an ASIP: A Case Study [p. 802]
Paschalis, A.
Low-Cost Software-Based Self-Testing of RISC Processor Cores [p. 714]
Passerone, C.
Hardware/Software Design Space Exploration for a Reconfigurable Processor [p. 570]
Pastor, E.
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems [p. 1158]
Patel, C.
Heterogeneous Programmable Logic Block Architectures [p. 1118]
Paul, J.
Layered, Multi-Threaded, High-Level Performance Design [p. 954]
Paviot, Y.
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer [p. 550]
Pedram, M.
Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface [p. 694]
Pedram, M.
An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries [p. 1148]
Peh, L.
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems [p. 1150]
Peña, M.
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems [p. 1158]
Peng, Z.
Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems [p. 184]
Petrenko, A.
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations [p. 1154]
Petrov, P.
Power Efficiency through Application-Specific Instruction Memory Transformations [p. 30]
Philippe, J.
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs [p. 674]
Pileggi, L.
Noise Macromodel for Radio Frequency Integrated Circuits [p. 150]
Pileggi, L.
Heterogeneous Programmable Logic Block Architectures [p. 1118]
Pillai, S.
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling [p. 422]
Pino, J.
Multithreaded Synchronous Data Flow Simulation [p. 1094]
Piñuel, L.
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms [p. 516]
Platzner, M.
Online Scheduling for Block-Partitioned Reconfigurable Devices [p. 290]
Polian, I.
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST [p. 1184]
Pomeranz, I.
A New Approach to Test Generation and Test Compaction for Scan Circuits [p. 1000]
Pomeranz, I.
On the Characterization of Hard-To-Detect Bridging Faults [p. 1012]
Pomeranz, I.
Test Data Compression Based on Output Dependence [p. 1186]
Poncino, M.
Improving the Efficiency of Memory Partitioning by Address Clustering [p. 18]
Pop, P.
Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems [p. 184]
Poppe, A.
A Fast Algorithm for the Layout Based Electro-Thermal Simulation [p. 1032]
Posadas, H.
Systematic Embedded Software Generation from SystemC [p. 142]
Pradhan, D.
EBIST: A Novel Test Generator with Built-In Fault Detection Capability [p. 224]
Pursche, U.
RF-BIST: Loopback Spectral Signature Analysis [p. 478]

Q

Qin, W.
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation [p. 556]
Quer, S.
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals [p. 898]
Quevremont, J.
Embedded Software in Digital AM-FM Chipset [p. 340]

R

Radulescu, A.
Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip [p. 350]
Raghunathan, A.
Energy Estimation for Extensible Processors [p. 682]
Raghunathan, A.
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems [p. 706]
Raghunathan, A.
Software Architectural Transformations: A New Approach to Low Energy Embedded Software [p. 1046]
Rao, W.
Virtual Compression through Test Vector Stitching for Scan Based Design [p. 104]
Rapaka, V.
Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications [p. 504]
Ravi, S.
Energy Estimation for Extensible Processors [p. 682]
Ravi, S.
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems [p. 706]
Rebaudengo, M.
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor [p. 602]
Rebaudengo, M.
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories [p. 720]
Reddy, S.
A New Approach to Test Generation and Test Compaction for Scan Circuits [p. 1000]
Reddy, S.
On the Characterization of Hard-To-Detect Bridging Faults [p. 1012]
Reddy, S.
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST [p. 1184]
Reddy, S.
Test Data Compression Based on Output Dependence [p. 1186]
Reese, R.
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs [p. 1096]
Reeves, N.
Dynamic Functional Unit Assignment for Low Power [p. 1052]
Reis, R.
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues [p. 940]
Rencz, M.
A Fast Algorithm for the Layout Based Electro-Thermal Simulation [p. 1032]
Rettberg, A.
A Fully Self-Timed Bit-Serial Pipeline-Architecture for Embedded Systems [p. 1130]
Richardson, A.
Techniques for Automatic on Chip Closed Loop Transfer Function Monitoring for Embedded Charge Pump Phase Locked Loops [p. 496]
Richter, D.
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation [p. 484]
Rijpkema, E.
Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip [p. 350]
Rinner, B.
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures [p. 204]
Robins, G.
Area Fill Generation with Inherent Data Volume Reduction [p. 868]
Rodríguez-Vázquez, A.
Behavioural Modelling and Simulation of Delta-Sigma Modulators Using Hardware Description Languages [p. 168]
Romano, L.
FPGA-Based Implementation of a Serial RSA Processor [p. 582]
Rong, P.
An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries [p. 1148]
Roovers, R.
IC Design Challenges for Ambient Intelligence [p. 2]
Rosenstiel, W.
Instruction Set Emulation for Rapid Prototyping of SoCs [p. 562]
Rosien, M.
Mapping Applications to an FPFA Tile [p. 1124]
Rossi, D.
High Speed and Highly Testable Parallel Two -Rail Code Checker [p. 608]
Roy, K.
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology [p. 778]
Roy, K.
A New Crosstalk Noise Model for DOMINO Logic Circuits [p. 1112]
Roy, K.
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies [p. 1160]
Roy, K.
Synthesis of Application-Specific Highly Efficient Multi-Mode Systems for Low-Power Applications [p. 96]
Roy, K.
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters [p. 700]
Roychoudhury, A.
Using Formal Techniques to Debug the AMBA System-On-Chip Bus Protocol [p. 828]
Rusakov, S.
Approximation Approach for Timing Jitter Characterization in Circuit Simulators [p. 156]
Rusakov, S.
A New Simulation Technique for Periodic Small-Signal Analysis [p. 244]
Ryu, K.
Automated Bus Generation for Multiprocessor SoC Design [p. 282]

S

Sachdev, M.
DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers [p. 212]
Saggese, G.
FPGA-Based Implementation of a Serial RSA Processor [p. 582]
Saito, H.
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units [p. 276]
Salem, A.
Formal Semantics of Synchronous SystemC [p. 376]
Salice, F.
A First Step Towards HW/SW Partitioning of UML Specifications [p. 668]
Salice, F.
Library Functions Timing Characterization for Source-Level Analysis [p. 1132]
Sánchez, P.
Systematic Embedded Software Generation from SystemC [p. 142]
Sánchez-Élez, M.
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures [p. 36]
Sander, I.
Development and Application of Design Transformations in ForSyDe [p. 364]
Sangiovanni-Vincentelli, A.
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations [p. 1154]
Sansen, W.
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors [p. 238]
Sansen, W.
Generalized Posynomial Performance Modeling [p. 250]
Santos, M.
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST [p. 994]
Saputra, H.
Masking the Energy Behavior of DES Encryption [p. 84]
Sarlotte, M.
Embedded Software in Digital AM-FM Chipset [p. 340]
Schanstra, I.
Consequences of RAM Bitline Twisting for Test Coverage [p. 1176]
Schattkowsky, T.
Dynamic Tool Integration in Heterogeneous Computer Networks [p. 946]
Schliebusch, O.
Processor/Memory Co-Exploration on Multiple Abstraction Levels [p. 966]
Schmid, M.
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures [p. 204]
Schmit, H.
Heterogeneous Programmable Logic Block Architectures [p. 1118]
Schmitz, M.
A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities [p. 960]
Schneider, K.
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration [p. 196]
Schnerr, J.
Instruction Set Emulation for Rapid Prototyping of SoCs [p. 562]
Schrage, J.
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects [p. 1110]
Schweizer, S.
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization [p. [p. 1188]
Sciuto, D.
Library Functions Timing Characterization for Source-Level Analysis [p. 1132]
Seidl, U.
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information [p. 770]
Sezer, U.
Generalized Data Transformations for Enhancing Cache Behavior [p. 906]
Sheng, S.
Efficient Preimage Computation Using a Novel Success-Driven ATPG [p. 822]
Shi, R.
Symbolic Analysis of Nonlinear Analog Circuits [p. 1108]
Shukla, S.
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated [p. 382]
Shukla, S.
Polychrony for Refinement-Based Design [p. 1172]
Silva, M.
Run-Time Management of Logic Resources on Reconfigurable Systems [p. 974]
Singh, S.
System Level Specification in Lava [p. 370]
Sirisantana, N.
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies [p. 1160]
Smey, R.
Crosstalk Reduction in Area Routing [p. 862]
Smit, G.
Mapping Applications to an FPFA Tile [p. 1124]
Sokolov, D.
STG Optimisation in the Direct Mapping of Asynchronous Circuits [p. 932]
Sonza Reorda, M.
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor [p. 602]
Sonza Reorda, M.
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories [p. 720]
Sonza Reorda, M.
Fully Automatic Test Program Generation for Microprocessor Cores [p. 1006]
Sproch, J.
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture [p. 110]
Squillero, G.
Fully Automatic Test Program Generation for Microprocessor Cores [p. 1006]
Stievano, I.
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices [p. 536]
Stoffel, D.
Using RTL Statespace Information and State Encoding for Induction Based Property Checking [p. 1156]
Stübbe, O.
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects [p. 1110]
Surendra, G.
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation [p. 784]
Swartz, B.
Crosstalk Reduction in Area Routing [p. 862]
Syal, M.
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification [p. 316]
Székely, V.
A Fast Algorithm for the Layout Based Electro-Thermal Simulation [p. 1032]

T

Talpin, J.
Polychrony for Refinement-Based Design [p. 1172]
Tan, T.
Software Architectural Transformations: A New Approach to Low Energy Embedded Software [p. 1046]
Tarnick, S.
Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes [p. 1162]
Tehranipour, M.
Extending JTAG for Testing Signal Integrity in SoCs [p. 218]
Teich, J.
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects [p. 1110]
Teich, J.
SAT-Based Techniques in System Synthesis [p. 1168]
Teixeira, I.
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST [p. 994]
Teixeira, J.
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST [p. 994]
Thiele, L.
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs [p. 190]
Thomas, A.
An Industrial/Academic Configurable System-On-Chip Project (CSoC): Coarse-Grain XPP-/Leon-Based Architecture Integration [p. 1120]
Thomas, D.
Layered, Multi-Threaded, High-Level Performance Design [p. 954]
Thornton, M.
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs [p. 1096]
Thul, M.
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors [p. 356]
Tijou, J.
Techniques for Automatic on Chip Closed Loop Transfer Function Monitoring for Embedded Charge Pump Phase Locked Loops [p. 496]
Tindell, K.
Safe Automotive Software Development [p. 616]
Tirumurti, C.
On Modeling Cross-Talk Faults [p. 490]
Tong, K.
Heterogeneous Programmable Logic Block Architectures [p. 1118]
Tragoudas, S.
Non-Enumerative Path Delay Fault Diagnosis [p. 322]

U

Ulyanov, S.
Approximation Approach for Timing Jitter Characterization in Circuit Simulators [p. 156]
Ulyanov, S.
A New Simulation Technique for Periodic Small-Signal Analysis [p. 244]

V

Vachoux, A.
SystemC-AMS Requirements, Design Objectives and Rationale [p. 388]
van de Goor, A.
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation [p. 484]
van de Goor, J.
Consequences of RAM Bitline Twisting for Test Coverage [p. 1176]
van der Wolf, P.
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs [p. 656]
van Meerbergen, J.
Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip [p. 350]
Vanassche, P.
A New Simulation Technique for Periodic Small-Signal Analysis [p. 244]
Vandersteen, G.
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits [p. 624]
Vandersteen, G.
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver [p. 642]
Vanzago, L.
Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform [p. 662]
Veidenbaum, A.
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors [p. 1064]
Velenis, D.
Reduced Delay Uncertainty in High Performance Clock Distribution Networks [p. 68]
Verkest, D.
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling [p. 296]
Verkest, D.
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-On-Chip [p. 986]
Vernalde, S.
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling [p. 296]
Vernalde, S.
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-On-Chip [p. 986]
Vijaykrishnan, N.
Compiler Support for Reducing Leakage Energy Consumption [p. 1146]
Vijaykrishnan, S.
Masking the Energy Behavior of DES Encryption [p. 84]
Vijaykumar, T.
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology [p. 778]
Villa, T.
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations [p. 1154]
Villar, E.
Systematic Embedded Software Generation from SystemC [p. 142]
Violante, M.
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor [p. 602]
Violante, M.
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories [p. 720]
Vissers, K.
Parallel Processing Architectures for Reconfigurable Systems [p. 396]
Visweswariah, C.
Time Budgeting in a Wireplanning Context [p. 436]
Vogels, M.
Figure of Merit Based Selection of A/D Converters [p. 1190]
Vorbach, M.
An Industrial/Academic Configurable System-On-Chip Project (CSoC): Coarse-Grain XPP-/Leon-Based Architecture Integration [p. 1120]
Vrudhula, S.
Statistical Timing Analysis Using Bounds [p. 62]

W

Wai, S.
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees [p. 856]
Walder, H.
Online Scheduling for Block-Partitioned Reconfigurable Devices [p. 290]
Waldschmidt, K.
Refinement of Mixed-Signal Systems with SystemC [p. 1170]
Wambacq, P.
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits [p. 624]
Wambacq, P.
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver [p. 642]
Wang, K.
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique [p. 850]
Wang, L.
Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step [p. 328]
Wang, L.
A Circuit SAT Solver with Signal Correlation Guided Learning [p. 892]
Wang, S.
Modeling and Integration of Peripheral Devices in Embedded Systems [p. 136]
Wang, Z.
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching [p. 1026]
Watanabe, Y.
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling [p. 428]
Watanabe, Y.
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula [p. 1174]
Waterlander, E.
Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip [p. 350]
Wedler, M.
Using RTL Statespace Information and State Encoding for Induction Based Property Checking [p. 1156]
Wegener, C.
Linear Model-Based Error Identification and Calibration for Data Converters [p. 630]
Wegner, J.
Dynamic Tool Integration in Heterogeneous Computer Networks [p. 946]
Wehn, N.
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors [p. 356]
Weinhardt, M.
From C Programs to the Configure-Execute Model [p. 576]
Weiss, R.
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures [p. 204]
Westra, J.
Time Budgeting in a Wireplanning Context [p. 436]
Weyer, D.
A Technique for High Ratio LZW Compression [p. 116]
Wieferink, A.
Processor/Memory Co-Exploration on Multiple Abstraction Levels [p. 966]
Wielage, P.
Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip [p. 350]
Williams, T.
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture [p. 110]
Wolf, F.
Safe Automotive Software Development [p. 616]
Wolf, W.
Profile-Driven Selective Code Compression [p. 462]
Wolf, W.
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses [p. 542]
Wolff, F.
A Technique for High Ratio LZW Compression [p. 116]
Wong, D.
Global Wire Bus Configuration with Minimum Delay Uncertainty [p. 50]
Wu, A.
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs [p. 1102]
Wu, A.
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer [p. 1134]
Wu, D.
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems [p. 90]

X

Xenoulis, G.
Low-Cost Software-Based Self-Testing of RISC Processor Cores [p. 714]
Xie, Y.
Profile-Driven Selective Code Compression [p. 462]
Xu, Q.
Delay Fault Testing of Core-Based Systems-On-A-Chip [p. 744]
Xu, Y.
Noise Macromodel for Radio Frequency Integrated Circuits [p. 150]

Y

Yakovlev, A.
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design [p. 926]
Yakovlev, A.
STG Optimisation in the Direct Mapping of Asynchronous Circuits [p. 932]
Yang, X.
A Secure Web-Based Framework for Electronic System Level Design [p. 1140]
Ye, T.
Packetized On-Chip Interconnect Communication Analysis for MPSoC [p. 344]
Yevtushenko, N.
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations [p. 1154]
Yoo, S.
Introduction to Hardware Abstraction Layers for SoC [p. 336]
Yoo, S.
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer [p. 550]
Young, E.
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees [p. 856]
Yu, H.
RTOS Modeling for System Level Design [p. 130]

Z

Zachariah, S.
On Modeling Cross-Talk Faults [p. 490]
Zafalon, R.
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors [p. 24]
Zambaldi, M.
Platform Based Testbench Generation [p. 1038]
Zampella, L.
A First Step Towards HW/SW Partitioning of UML Specifications [p. 668]
Zanella, M.
A Fully Self-Timed Bit-Serial Pipeline-Architecture for Embedded Systems [p. 1130]
Zelikovsky, A.
Area Fill Generation with Inherent Data Volume Reduction [p. 868]
Zeng, Z.
Fast Computation of Data Correlation Using BDDs [p. 122]
Zhang, L.
Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and other Applications [p. 880]
Zhang, Q.
Fast Computation of Data Correlation Using BDDs [p. 122]
Zhang, W.
Masking the Energy Behavior of DES Encryption [p. 84]
Zhang, W.
Data Space Oriented Scheduling in Embedded Systems [p. 416]
Zhang, W.
Runtime Code Parallelization for On-Chip Multiprocessors [p. 510]
Zhang, W.
Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy [p. 1058]
Zhang, W.
Compiler Support for Reducing Leakage Energy Consumption [p. 1146]
Zhang, Y.
Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems [p. 918]
Zharov, M.
Approximation Approach for Timing Jitter Characterization in Circuit Simulators [p. 156]
Zharov, M.
A New Simulation Technique for Periodic Small-Signal Analysis [p. 244]
Zheng, Y.
Area Fill Generation with Inherent Data Volume Reduction [p. 868]
Zhou, H.
Timing Verification with Crosstalk for Transparently Latched Circuits [p. 56]
Zhu, J.
Specification of Non-Functional Intellectual Property Components [p. 456]
Zhu, J.
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching [p. 1026]
Zinn, A.
Platform Based Testbench Generation [p. 1038]
Ziv, A.
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions [p. 834]
Zivkovic, V.
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs [p. 656]
Zolotov, V.
Statistical Timing Analysis Using Bounds [p. 62]
Zorian, Y.
Low-Cost Software-Based Self-Testing of RISC Processor Cores [p. 714]
Zwolinski, M.
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric [p. 596]