DATE 2000 Author Index

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Acosta, A.
A VHDL-based Methodology for Design and Verification of Pipeline A/D Converters [p. 534]

Adler, T.
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications [p. 446]

Agrawal, V.
Reducing the Complexity of Defect Level Modeling using the Clustering Effect [p. 640]

Al-Hashimi, B.
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits [p. 715]

Aloul, F.
An Experimental Study of Satisfiability Search Heuristics [p. 745]

Altenbernd, P.
From High-Level Specifications down to Software Implementations of Parallel Embedded Real-Time Systems [p. 686]

Anghel, L.
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique [p. 591]

Antreich, K.
The Generalized Boundary Curve -- A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits [p. 42]

Arapoyanni, A.
A Versatile Built-In Self Test Scheme for Delay Fault Testing [p. 756]

Azaïs, F .
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter [p. 226]

Aziz, A.
Automatic Lighthouse Generation for Directed State Space Search [p. 237]
Meeting Delay Constraints in DSM by Minimal Repeater Insertion [p. 436]

B

Bach, P.
Structural Testing on Real Boards [p. 741]

Balarin, F.
Automatic Abstraction for Worst-Case Analysis of Discrete Systems [p. 494]

Baleani, M.
HW/SW Codesign of an Engine Management System [p. 263]

Banerjee, P.
A System-Level Synthesis Algorithm with Guaranteed Solution Quality [p. 417]

Barke, E.
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications [p. 446]
Static Timing Analysis Taking Crosstalk into Account [p. 451]

Bayraktaroglu, I.
Test Synthesis for Mixed-Signal SOC Paths [p. 128]

Bech, T.
Testing Arithmetic Coprocessor in System Environment [p. 752]

Becker, B.
On the Generation of Multiplexer Circuits for Pass Transistor Logic [p. 372]

Ben-Hamida, N.
Parametric Fault Simulation and Test Vector Generation [p. 650]

Benabdenebi, M.
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip [p. 141]

Benini, L.
Quantitative Comparison of Power Management Algorithms [p. 20]
A Discrete-Time Battery Model for High-Level Power Estimation [p. 35]
Virtual Fault Simulation of Distributed IP-based Designs [p. 99]
Dynamic Power Management of Laptop Hard Disk [p. 736]

Bergfeld, T.
Diagnostic Testing of Embedded Memories using BIST [p. 305]

Berkelaar, M.
Gate Sizing using a Statistical Delay Model [p. 283]

Bertrand, Y.
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter [p. 226]

Bhattacharyya, S.
Shared Memory Implementations of Synchronous Dataflow Specification [p. 404]

Bjurèus, P.
Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors [p. 154]
MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow [p. 161]

Bogliolo, A.
Virtual Fault Simulation of Distributed IP-based Designs [p. 99]

Bolsens, I.
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits [p. 350]

Bosch, M.
Structural Testing on Real Boards [p. 741]

Bourai, Y.
Layout Compaction for Yield Optimization via Critical Area Minimization [p. 122]

Brenner, U.
Faster Optimal Single-Row Placement with Fixed Ordering [p. 117]

Bringmann, O.
Target Architecture Oriented High-Level Synthesis for Multi-FPGA based Emulation [p. 326]

C

Calvo, R.
An Efficient Heuristic Approach to Solve the Unate Covering Problem [p. 364]

Carletta, J.
Detecting Undetectable Controller Faults using Power Analysis [p. 723]

Carpenter, A.
A Web-based System for Assessing and Searching for Designs [p. 755]

Carro, L.
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter [p. 226]
Non-Linear Components for Mixed Circuits Analog Front-End [p. 544]
System Synthesis for Multiprocessor Embedded Applications [p. 697]
System Design based on Single Language and Single-Chip Java ASIP Microcontroller [p. 703]

Castelli, G.
A Discrete-Time Battery Model for High-Level Power Estimation [p. 35]

Cataldo, S.
Optimal Hardware Pattern Generation for Functional BIST [p. 292]

Catthoor, F.
Analysis of High-Level Address Code Transformations for Programmable Processors [p. 9]
Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications [p. 92]

Chakraborty, K.
Transformational Placement and Synthesis [p. 194]

Chang, N.
Clocktree RLC Extraction with Efficient Inductance Modeling [p. 522]

Chang, S.
A Memory Architecture with 4-Address Configurations for Video Signal Processing [p. 746]

Chen, G.
All Digital Built-In Delay and Crosstalk Measurement for On-Chip Buses [p. 527]

Chen, Y.
All Digital Built-In Delay and Crosstalk Measurement for On-Chip Buses [p. 527]

Cheng, K.
A BIST Scheme for On-Chip ADC and DAC Testing [p. 216]

Chiusano, S.
Optimal Hardware Pattern Generation for Functional BIST [p. 292]

Cho, Y.
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor [p. 663]

Choi, K.
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor [p. 663]

Choudhary, A.
A System-Level Synthesis Algorithm with Guaranteed Solution Quality [p. 417]

Chung, E.
Quantitative Comparison of Power Management Algorithms [p. 20]

Ciesielski, M.
A BDD-based Satisfiability Infrastructure using the Unate Recursive Paradigm [p. 232]
Synthesis for Mixed CMOS/PTL Logic [p. 750]

Ciric, J.
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation using Clock-Delayed Domino Logic [p. 277]

Cordone, R.
An Efficient Heuristic Approach to Solve the Unate Covering Problem [p. 364]

Cornea, R.
Architecture Exploration of Parameterizable EPIC SOC Architectures [p. 748]

Corno, F.
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience [p. 385]

Cota, E.
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter [p. 226]

D

da Silva, J.
Mixed-Signal BIST using Correlation and Reconfigurable Hardware [p. 744]

Dalpasso, M.
Virtual Fault Simulation of Distributed IP-based Designs [p. 99]

Date, H.
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach [p. 134]

de Jong, G.
Standards for System-Level Design: Practical Reality or Solution in Search of a Question? [p. 576]
An Incremental Specification Flow for Real Time Embedded Systems [p. 761]

De Man, H.
Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications [p. 92]

De Micheli, G.
Quantitative Comparison of Power Management Algorithms [p. 20]
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C [p. 312]
Dynamic Power Management of Laptop Hard Disk [p. 736]

de Sousa, J.
Reducing the Complexity of Defect Level Modeling using the Clustering Effect [p. 640]

Demir, A.
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits [p. 340]

Dessouky, M.
Layout-Oriented Synthesis of High Performance Analog Circuits [p. 53]

Dey, S.
Efficient Power Co-Estimation Techniques for System-On-Chip Design [p. 27]

Díez, J.
Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion [p. 645]

Director, S.
An Integrated Design Environment for Early Stage Conceptual Design [p. 754]

Dobrovolný, P.
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits [p. 350]

Domínguez, S.
A Flexibile Specification Framework for Hardware-Software Codesign [p. 753]

Domínguez-Castro, R.
XFridge: A SPICE-based, Portable, User-Friendly Cell-Level Sizing Tool [p. 739]

Donath, W.
Transformational Placement and Synthesis [p. 194]

Donnay, S.
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits [p. 350]

Dorey, A.
A Fault Simulation Methodology for MEMS [p. 476]

Drozd, A.
Efficient Method of Failure Detection in Iterative Array Multiplier [p. 764]

Duarte, J.
Mixed-Signal BIST using Correlation and Reconfigurable Hardware [p. 744]

Dubrova, E.
TOP: An Algorithm for Three-Level Optimization of PLDs [p. 751]

Dutt, N.
Architecture Exploration of Parameterizable EPIC SOC Architectures [p. 748]

E

Edwards, M.
An Object Oriented Design Method for Reconfigurable Computing Systems [p. 692]

Eles, P.
Bus Access Optimization for Distributed Embedded Systems based on Schedulability Analysis [p. 567]

Ellerve, P.
TOP: An Algorithm for Three-Level Optimization of PLDs [p. 751]

Engels, M.
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits [p. 350]

F

Favalli, M.
Virtual Fault Simulation of Distributed IP-based Designs [p. 99]
On-Line Testing and Diagnosis of Bus Lines with Respect to Intermediate Voltage Values [p. 763]

Feldmann, P.
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits [p. 340]

Fernández, F.
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits [p. 48]
XFridge: A SPICE-based, Portable, User-Friendly Cell-Level Sizing Tool [p. 739]

Ferrandi, F.
An Efficient Heuristic Approach to Solve the Unate Covering Problem [p. 364]

Ferrari, A.
HW/SW Codesign of an Engine Management System [p. 263]

Fin, A.
A VHDL Error Simulator for Functional Test Generation [p. 390]

Fleischmann, J.
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level [p. 679]

Franco, D.
Non-Linear Components for Mixed Circuits Analog Front-End [p. 544]

Fröhlich, N.
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level [p. 679]

Fummi, F.
A VHDL Error Simulator for Functional Test Generation [p. 390]

Furey, D.
Delay-Insensitive Interface Specification and Synthesis [p. 169]

G

Ganesan, S.
Technology Mapping and Retargeting for Field-Programmable Analog Arrays [p. 58]
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement [p. 320]

Gao, Y.
Wire-Sizing for Delay Minimization and Ringing Control using Transmission Line Model [p. 512]

Gauthier, L.
Cycle-True Simulation of the ST10 Microcontroller [p. 742]

Girola, U.
Smart Antenna Receiver based on a Single Chip Solution for GSM/DCS Baseband Processing [p. 181]

Givargis, T.
Techniques for Reducing Read Latency of Core Bus Wrappers [p. 84]
Fast Cache and Bus Power Estimation for Parameterized System-On-A-Chip Design [p. 333]

Gizopoulos, D.
Effective Low Power BIST for Datapaths [p. 757]

Glöckel, V.
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level [p. 679]

Glynn, P.
Dynamic Power Management of Laptop Hard Disk [p. 736]

Goodby, L.
Test Quality and Fault Risk in Digital Filter Datapath BIST [p. 468]

Gourary, M.
A New Approach for Computation of Timing Jitter in Phase Locked Loops [p. 345]

Govindarajan, S.
Improving the Schedule Quality of Static-List Time-Constrained Scheduling [p. 749]

Graeb, H.
The Generalized Boundary Curve -- A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits [p. 42]

Grajal, J.
Constraint-Driven System Partitioning [p. 411]

Green, P.
An Object Oriented Design Method for Reconfigurable Computing Systems [p. 692]

Greiner, A.
A Generic Architecture for On-Chip Packet-Switched Interconnections [p. 250]

Grun, P.
Architecture Exploration of Parameterizable EPIC SOC Architectures [p. 748]

Guerra, O.
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits [p. 48]

Guerrier, P.
A Generic Architecture for On-Chip Packet-Switched Interconnections [p. 250]

Gullapalli, K.
A New Approach for Computation of Timing Jitter in Phase Locked Loops [p. 345]

Gulrajani, K.
Multi-Node Static Logic Implications for Redundancy Identification [p. 729]

Gupta, R.
Analysis of High-Level Address Code Transformations for Programmable Processors [p. 9]
System Level Online Power Management Algorithms [p. 606]

Gupta, S.
Analysis of High-Level Address Code Transformations for Programmable Processors [p. 9]

H

Hachtel, G.
Iterative Abstraction-based CTL Model Checking [p. 502]

Halambi, A.
Architecture Exploration of Parameterizable EPIC SOC Architectures [p. 748]

Hammerschmidt, D.
Detection of Defective Sensor Elements using sigma-delta-Modulation and a Matched Filter [p. 599]

Haniotakis, T.
A Versatile Built-In Self Test Scheme for Delay Fault Testing [p. 756]

Harmsze, F.
Memory Arbitration and Cache Management in Stream-based Systems [p. 257]

Haug, G.
A Hardware Platform for VLIW based Emulation of Digital Designs [p. 747]

He, L.
Clocktree RLC Extraction with Efficient Inductance Modeling [p. 522]

Henkel, J.
Fast Cache and Bus Power Estimation for Parameterized System-On-A-Chip Design [p. 333]

Hergenhan, A.
Static Timing Analysis of Embedded Software on Advanced Processor Architectures [p. 552]

Hirose, K.
A Bus Delay Reduction Technique Considering Crosstalk [p. 441]

Hoffmann, A.
Retargeting of Compiled Simulators for Digital Signal Processors using a Machine Description Language [p. 669]

Hoffmann, D.
Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits [p. 758]

Hosticka, B.
Detection of Defective Sensor Elements using sigma-delta-Modulation and a Matched Filter [p. 599]

Hsiao, M.
Multi-Node Static Logic Implications for Redundancy Identification [p. 729]

Hsieh, C.
Architectural Power Optimization by Bus Splitting [p. 612]

Huang, C.
A BDD-based Satisfiability Infrastructure using the Unate Recursive Paradigm [p. 232]

Huang, J.
A BIST Scheme for On-Chip ADC and DAC Testing [p. 216]

Huang, M.
All Digital Built-In Delay and Crosstalk Measurement for On-Chip Buses [p. 527]

Huertas, J.
A VHDL-based Methodology for Design and Verification of Pipeline A/D Converters [p. 534]

I

Ishihara, T.
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors [p. 617]

Ito, S.
System Design based on Single Language and Single-Chip Java ASIP Microcontroller [p. 703]

J

Jacobi, R.
System Design based on Single Language and Single-Chip Java ASIP Microcontroller [p. 703]

Jacobs, E.
Gate Sizing using a Statistical Delay Model [p. 283]

Jahn, G.
Non-Linear Components for Mixed Circuits Analog Front-End [p. 544]

Jang, J.
Iterative Abstraction-based CTL Model Checking [p. 502]

Jantsch, A.
Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors [p. 154]
MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow [p. 161]

Jerraya, A.
Cycle-True Simulation of the ST10 Microcontroller [p. 742]

Jochens, G.
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints [p. 737]

Josephs, M.
Delay-Insensitive Interface Specification and Synthesis [p. 169]

Jung, J.
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor [p. 663]

K

Kac, U.
Alternative Test Methods using IEEE 1149.4 [p. 463]

Kahn, H.
A Web-based System for Assessing and Searching for Designs [p. 755]

Kalla, P.
A BDD-based Satisfiability Infrastructure using the Unate Recursive Paradigm [p. 232]

Kaminska, B.
Parametric Fault Simulation and Test Vector Generation [p. 650]

Kebschull, U.
A Hardware Platform for VLIW based Emulation of Digital Designs [p. 747]

Kennedy, M.
Incorporation of Hard-Fault-Coverage in Model-based Testing of Mixed-Signal ICs [p. 765]

Kerkhoff, H.
Design and Test Space Exploration of Transport-Triggered Architectures [p. 146]

Kim, C.
Free MDD-based Software Optimization Techniques for Embedded Systems [p. 14]

Kim, J.
On Applying Incremental Satisfiability to Delay Fault Testing [p. 380]

A Memory Architecture with 4-Address Configurations for Video Signal Processing [p. 746]

Kim, L.
A Memory Architecture with 4-Address Configurations for Video Signal Processing [p. 746]

Kim, T.
A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects [p. 458]

Kleine, U.
Area Optimization of Analog Circuits Considering Matching Constraints [p. 738]

Kranitis, N.
Effective Low Power BIST for Datapaths [p. 757]

Kravets, V.
Constructive Library-Aware Synthesis using Symmetries [p. 208]

Kreutz, M.
System Synthesis for Multiprocessor Embedded Applications [p. 697]

Kropf, T.
Analyzing Real-Time Systems [p. 243]
Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits [p. 758]

Kruse, L.
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints [p. 737]

Kudva, P.
Transformational Placement and Synthesis [p. 194]

Kumthekar, B.
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs [p. 202]

L

Lajolo, M.
Efficient Power Co-Estimation Techniques for System-On-Chip Design [p. 27]
Evaluating System Dependability in a Co-Design Framework [p. 586]

Lavagno, L.
Free MDD-based Software Optimization Techniques for Embedded Systems [p. 14]
Efficient Power Co-Estimation Techniques for System-On-Chip Design [p. 27]
Evaluating System Dependability in a Co-Design Framework [p. 586]

Lee, C.
All Digital Built-In Delay and Crosstalk Measurement for On-Chip Buses [p. 527]

Lee, J.
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor [p. 663]

Lee, K.
An On Chip ADC Test Structure [p. 221]

Leupers, R.
Code Selection for Media Processors with SIMD Instructions [p. 4]

Lin, S.
Clocktree RLC Extraction with Efficient Inductance Modeling [p. 522]

Lindenkreuz, T.
Static Timing Analysis Taking Crosstalk into Account [p. 451]

Liu, I.
Meeting Delay Constraints in DSM by Minimal Repeater Insertion [p. 436]

Logothetis, G.
Abstraction from Counters: An Application on Real-Time Systems [p. 486]

López, J.
Constraint-Driven System Partitioning [p. 411]
Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion [p. 645]
A Flexibile Specification Framework for Hardware-Software Codesign [p. 753]

López-Vallejo, M.
Constraint-Driven System Partitioning [p. 411]

Louërat, M.
Layout-Oriented Synthesis of High Performance Analog Circuits [p. 53]

Lu, J.
Cost and Benefit Models for Logic and Memory BIST [p. 710]

Lu, Y.
Quantitative Comparison of Power Management Algorithms [p. 20]

Lubaszewski, M.
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter [p. 226]

Lungeanu, D.
Parallel and Distributed VHDL Simulation [p. 658]

Lysecky, R.
Techniques for Reducing Read Latency of Core Bus Wrappers [p. 84]

M

Macchiarulo, L.
Wave Steered FSMs [p. 270]

Macek, S.
Alternative Test Methods using IEEE 1149.4 [p. 463]

Machul, O.
Detection of Defective Sensor Elements using sigma-delta-Modulation and a Matched Filter [p. 599]

Macii, A.
A Discrete-Time Battery Model for High-Level Power Estimation [p. 35]

Macii, E.
A Discrete-Time Battery Model for High-Level Power Estimation [p. 35]

Manquinho, V.
On using Satisfiability-based Pruning Techniques in Covering Algorithms [p. 356]

Manzone, A.
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience [p. 385]

Marek-Sadowska, M.
Wave Steered FSMs [p. 270]

Maroufi, W.
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip [p. 141]

Marques-Silva, J.
On using Satisfiability-based Pruning Techniques in Covering Algorithms [p. 356]
On Applying Incremental Satisfiability to Delay Fault Testing [p. 380]
An Experimental Study of Satisfiability Search Heuristics [p. 745]

Marzouki, M.
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip [p. 141]

Masera, G.
A 50 Mbit/s Iterative Turbo-Decoder [p. 176]

Matos, J.
Mixed-Signal BIST using Correlation and Reconfigurable Hardware [p. 744]

Maurer, P.
Logic Simulation using Networks of State Machines [p. 674]

Medeiro, F.
XFridge: A SPICE-based, Portable, User-Friendly Cell-Level Sizing Tool [p. 739]

Mehra, R.
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths [p. 624]

Menn, C.
Target Architecture Oriented High-Level Synthesis for Multi-FPGA based Emulation [p. 326]

Metra, C.
On-Line Testing and Diagnosis of Bus Lines with Respect to Intermediate Voltage Values [p. 763]

Meyr, H.
Retargeting of Compiled Simulators for Digital Signal Processors using a Machine Description Language [p. 669]

Miller, D.
TOP: An Algorithm for Three-Level Optimization of PLDs [p. 751]

Miranda, M.
Analysis of High-Level Address Code Transformations for Programmable Processors [p. 9]

Mirzoyan, L.
Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit under Check [p. 762]

Miyazaki, T.
Protocol Stack-based Telecom-Emulator [p. 186]

Montiel-Nelson, J.
A Single Phase Latch for High Speed GaAs Domino Circuits [p. 760]

Moon, I.
Iterative Abstraction-based CTL Model Checking [p. 502]

Morawiec, A.
Cycle-based Simulation Algorithms for Digital Systems using High-Level Decision Diagrams [p. 743]

Moya, F.
A Flexibile Specification Framework for Hardware-Software Codesign [p. 753]

Moya, J.
A Flexibile Specification Framework for Hardware-Software Codesign [p. 753]

Mulvaney, B.
A New Approach for Computation of Timing Jitter in Phase Locked Loops [p. 345]

Münch, M.
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths [p. 624]

Murooka, T.
Protocol Stack-based Telecom-Emulator [p. 186]

Murthy, P.
Shared Memory Implementations of Synchronous Dataflow Specification [p. 404]

Muzio, J.
TOP: An Algorithm for Three-Level Optimization of PLDs [p. 751]

N

Nakagawa, O.
Clocktree RLC Extraction with Efficient Inductance Modeling [p. 522]

Nassif, S.
Designing Closer to the Edge [p. 636]

Nebel, W.
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints [p. 737]

Negreiros, M.
Non-Linear Components for Mixed Circuits Analog Front-End [p. 544]

Nicolaidis, M.
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique [p. 591]

Nicolau, A.
Architecture Exploration of Parameterizable EPIC SOC Architectures [p. 748]

Nicolici, N.
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits [p. 715]

Niemegeers, A.
An Incremental Specification Flow for Real Time Embedded Systems [p. 761]

Niggemeyer, D.
Diagnostic Testing of Embedded Memories using BIST [p. 305]

Nikolos, D.
A Versatile Built-In Self Test Scheme for Delay Fault Testing [p. 756]

Nooshabadi, S.
A Single Phase Latch for High Speed GaAs Domino Circuits [p. 760]

Nourani, M.
Detecting Undetectable Controller Faults using Power Analysis [p. 723]

Novak, F.
Alternative Test Methods using IEEE 1149.4 [p. 463]

Núñez, A.
A Single Phase Latch for High Speed GaAs Domino Circuits [p. 760]

O

Ong, C.
A BIST Scheme for On-Chip ADC and DAC Testing [p. 216]

Orailoglu, A.
Test Synthesis for Mixed-Signal SOC Paths [p. 128]
Test Quality and Fault Risk in Digital Filter Datapath BIST [p. 468]

Ouaiss, I.
Efficient Resource Arbitration in Reconfigurable Computing Environments [p. 560]

Oyamada, M.
System Synthesis for Multiprocessor Embedded Applications [p. 697]

Ozev, S.
Test Synthesis for Mixed-Signal SOC Paths [p. 128]

P

Papachristou, C.
Detecting Undetectable Controller Faults using Power Analysis [p. 723]

Park, S.
A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects [p. 458]

Paschalis, A.
Effective Low Power BIST for Datapaths [p. 757]

Paulus, C.
Area Optimization of Analog Circuits Considering Matching Constraints [p. 738]

Pedram, M.
Architectural Power Optimization by Bus Splitting [p. 612]

Pees, S.
Retargeting of Compiled Simulators for Digital Signal Processors using a Machine Description Language [p. 669]

Peng, Z.
Bus Access Optimization for Distributed Embedded Systems based on Schedulability Analysis [p. 567]

Peralías, E.
A VHDL-based Methodology for Design and Verification of Pipeline A/D Converters [p. 534]

Pérez-Montes, F.
XFridge: A SPICE-based, Portable, User-Friendly Cell-Level Sizing Tool [p. 739]

Piccinini, G.
A 50 Mbit/s Iterative Turbo-Decoder [p. 176]

Picciriello, A.
Smart Antenna Receiver based on a Single Chip Solution for GSM/DCS Baseband Processing [p. 181]

Pillkahn, U.
Evaluation of Interconnects with TDR [p. 740]

Pincetti, A.
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience [p. 385]

Pomeranz, I.
Built-in Generation of Weighted Test Sequences for Synchronous Sequential Circuits [p. 298]
Functional Test Generation for Full Scan Circuits [p. 396]

Poncino, M.
A Discrete-Time Battery Model for High-Level Power Estimation [p. 35]

Pop, P.
Bus Access Optimization for Distributed Embedded Systems based on Schedulability Analysis [p. 567]

Porte, J.
Layout-Oriented Synthesis of High Performance Analog Circuits [p. 53]

Prinetto, P.
Optimal Hardware Pattern Generation for Functional BIST [p. 292]

Psarakis, M.
Effective Low Power BIST for Datapaths [p. 757]

R

Raghunathan, A.
Efficient Power Co-Estimation Techniques for System-On-Chip Design [p. 27]

Raik, J.
Cycle-based Simulation Algorithms for Digital Systems using High-Level Decision Diagrams [p. 743]

Ramanathan, D.
System Level Online Power Management Algorithms [p. 606]

Rebaudengo, M.
Evaluating System Dependability in a Co-Design Framework [p. 586]

Reddy, L.
Transformational Placement and Synthesis [p. 194]

Reddy, S.
Built-in Generation of Weighted Test Sequences for Synchronous Sequential Circuits [p. 298]
Functional Test Generation for Full Scan Circuits [p. 396]

Renovell, M.
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter [p. 226]

Rha, K.
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor [p. 663]

Riccò, B.
On-Line Testing and Diagnosis of Bus Lines with Respect to Intermediate Voltage Values [p. 763]

Richardson, A.
A Fault Simulation Methodology for MEMS [p. 476]

Ringe, M.
Static Timing Analysis Taking Crosstalk into Account [p. 451]

Roca, E.
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits [p. 48]

Roch, M.
A 50 Mbit/s Iterative Turbo-Decoder [p. 176]

Rodríguez-Vázquez, A.
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits [p. 48]
XFridge: A SPICE-based, Portable, User-Friendly Cell-Level Sizing Tool [p. 739]

Rosenstiel, W.
Target Architecture Oriented High-Level Synthesis for Multi-FPGA based Emulation [p. 326]
Static Timing Analysis of Embedded Software on Advanced Processor Architectures [p. 552]
A Hardware Platform for VLIW based Emulation of Digital Designs [p. 747]

Rosing, A.
A Fault Simulation Methodology for MEMS [p. 476]

Rudnick, E.
Diagnostic Testing of Embedded Memories using BIST [p. 305]

Rueda, A.
A VHDL-based Methodology for Design and Verification of Pipeline A/D Converters [p. 534]

Ruf, J.
Analyzing Real-Time Systems [p. 243]

Rusakov, S.
A New Approach for Computation of Timing Jitter in Phase Locked Loops [p. 345]

Rust, C.
From High-Level Specifications down to Software Implementations of Parallel Embedded Real-Time Systems [p. 686]

S

Saab, K.
Parametric Fault Simulation and Test Vector Generation [p. 650]

Saab, Y.
A New Effective and Efficient Multi-Level Partitioning Algorithm [p. 112]
Sakallah, K.
Constructive Library-Aware Synthesis using Symmetries [p. 208]
On Applying Incremental Satisfiability to Delay Fault Testing [p. 380]
An Experimental Study of Satisfiability Search Heuristics [p. 745]

Sangiovanni-Vincentelli, A.
Free MDD-based Software Optimization Techniques for Embedded Systems [p. 14]
HW/SW Codesign of an Engine Management System [p. 263]

Sato, K.
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C [p. 312]

Scarsi, R.
A Discrete-Time Battery Model for High-Level Power Estimation [p. 35]

Scheffler, M.
Assessing the Cost Effectiveness of Integrated Passives [p. 539]

Schenkel, F.
The Generalized Boundary Curve -- A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits [p. 42]

Schmidt, E.
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints [p. 737]

Schneider, K.
Abstraction from Counters: An Application on Real-Time Systems [p. 486]

Scholl, C.
On the Generation of Multiplexer Circuits for Pass Transistor Logic [p. 372]

Schönherr, J.
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level [p. 759]

Schwencker, R.
The Generalized Boundary Curve -- A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits [p. 42]

Sciuto, D.
An Efficient Heuristic Approach to Solve the Unate Covering Problem [p. 364]

Sechen, C.
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation using Clock-Delayed Domino Logic [p. 277]

Séméria, L.
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C [p. 312]

Sheehan, B.
Predicting Coupled Noise in RC Circuits [p. 517]

Shenoy, U.
A System-Level Synthesis Algorithm with Guaranteed Solution Quality [p. 417]

Shi, C.
Layout Compaction for Yield Optimization via Critical Area Minimization [p. 122]
Parallel and Distributed VHDL Simulation [p. 658]

Shu, S.
Wave Steered FSMs [p. 270]

Simunic, T.
Quantitative Comparison of Power Management Algorithms [p. 20]
Dynamic Power Management of Laptop Hard Disk [p. 736]

Singhal, V.
Automatic Lighthouse Generation for Directed State Space Search [p. 237]

Somenzi, F.
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs [p. 202]

Sonza Reorda, M.
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience [p. 385]
Evaluating System Dependability in a Co-Design Framework [p. 586]

Sosnowski, J.
Testing Arithmetic Coprocessor in System Environment [p. 752]

Souza Jr., A.
Non-Linear Components for Mixed Circuits Analog Front-End [p. 544]

Sproch, J.
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths [p. 624]

Squillero, G.
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience [p. 385]

Stammermann, A.
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints [p. 737]

Stappert, F.
From High-Level Specifications down to Software Implementations of Parallel Embedded Real-Time Systems [p. 686]

Stok, L.
Transformational Placement and Synthesis [p. 194]

Straube, B.
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level [p. 759]

Strolenberg, C.
Stay Away from Minimum Design-Rule Values [p. 71]

Su, C.
All Digital Built-In Delay and Crosstalk Measurement for On-Chip Buses [p. 527]

Sugihara, M.
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach [p. 134]

Sullivan, A.
Transformational Placement and Synthesis [p. 194]

T

Tacken, J.
From High-Level Specifications down to Software Implementations of Parallel Embedded Real-Time Systems [p. 686]

Tang, X.
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation [p. 106]

Tangelder, R.
Design and Test Space Exploration of Transport-Triggered Architectures [p. 146]

Thewes, R.
Area Optimization of Analog Circuits Considering Matching Constraints [p. 738]

Tian, R.
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation [p. 106]

Timmer, A.
Memory Arbitration and Cache Management in Stream-based Systems [p. 257]

Tröster, G.
Assessing the Cost Effectiveness of Integrated Passives [p. 539]

Tsiatouhas, Y.
A Versatile Built-In Self Test Scheme for Delay Fault Testing [p. 756]

Turchetti, C.
HW/SW Codesign of an Engine Management System [p. 263]

U

Ubar, R.
Cycle-based Simulation Algorithms for Digital Systems using High-Level Decision Diagrams [p. 743]

Ulyanov, S.
A New Approach for Computation of Timing Jitter in Phase Locked Loops [p. 345]

V

Vahid, F.
Techniques for Reducing Read Latency of Core Bus Wrappers [p. 84]
Fast Cache and Bus Power Estimation for Parameterized System-On-A-Chip Design [p. 333]

van Meerbergen, J.
Memory Arbitration and Cache Management in Stream-based Systems [p. 257]

Vardanian, V.
Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit under Check [p. 762]

Veelenturf, K.
The Road to better Reliability and Yield Embedded DfM Tools [p. 67]

Vemuri, R.
Technology Mapping and Retargeting for Field-Programmable Analog Arrays [p. 58]
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement [p. 320]
Efficient Resource Arbitration in Reconfigurable Computing Environments [p. 560]
Improving the Schedule Quality of Static-List Time-Constrained Scheduling [p. 749]

Verkest, D.
Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications [p. 92]

Vermeulen, F.
Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications [p. 92]

Viglione, F.
A 50 Mbit/s Iterative Turbo-Decoder [p. 176]

Villarrubia, P.
Transformational Placement and Synthesis [p. 194]

Vincenzoni, D .
Smart Antenna Receiver based on a Single Chip Solution for GSM/DCS Baseband Processing [p. 181]

Violante, M.
Evaluating System Dependability in a Co-Design Framework [p. 586]

Vygen, J.
Faster Optimal Single-Row Placement with Fixed Ordering [p. 117]

W

Wagner, F.
System Synthesis for Multiprocessor Embedded Applications [p. 697]

Wambacq, P.
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits [p. 350]

Wegener, C.
Incorporation of Hard-Fault-Coverage in Model-based Testing of Mixed-Signal ICs [p. 765]

Wehn, N.
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths [p. 624]

Weiler, D.
Detection of Defective Sensor Elements using sigma-delta-Modulation and a Matched Filter [p. 599]

Wen, Y.
An On Chip ADC Test Structure [p. 221]

Whitaker, N.
A Web-based System for Assessing and Searching for Designs [p. 755]

Whittemore, J.
On Applying Incremental Satisfiability to Delay Fault Testing [p. 380]

Wong, D.
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation [p. 106]
Meeting Delay Constraints in DSM by Minimal Repeater Insertion [p. 436]
Wire-Sizing for Delay Minimization and Ringing Control using Transmission Line Model [p. 512]

Wu, C.
Cost and Benefit Models for Logic and Memory BIST [p. 710]

Wunderlich, H.
Optimal Hardware Pattern Generation for Functional BIST [p. 292]

Wurth, B.
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths [p. 624]

X

Xie, W.
Clocktree RLC Extraction with Efficient Inductance Modeling [p. 522]

Y

Yalagandula, P.
Automatic Lighthouse Generation for Directed State Space Search [p. 237]

Yang, C.
Synthesis for Mixed CMOS/PTL Logic [p. 750]

Yasuura, H.
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach [p. 134]
A Bus Delay Reduction Technique Considering Crosstalk [p. 441]
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors [p. 617]

Yee, G.
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation using Clock-Delayed Domino Logic [p. 277]

Yoo, S.
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor [p. 663]

Z

Zamboni, M.
A 50 Mbit/s Iterative Turbo-Decoder [p. 176]

Zarnik, M.
Alternative Test Methods using IEEE 1149.4 [p. 463]

Zeng, Z.
A BDD-based Satisfiability Infrastructure using the Unate Recursive Paradigm [p. 232]

Zharov, M.
A New Approach for Computation of Timing Jitter in Phase Locked Loops [p. 345]

Zivkovic, V.
Design and Test Space Exploration of Transport-Triggered Architectures [p. 146]

Zorian, Y.
Yield Improvement and Repair Trade-Off for Large Embedded Memories [p. 69]
Effective Low Power BIST for Datapaths [p. 757]

Zuo, J.
An Integrated Design Environment for Early Stage Conceptual Design [p. 754]