DATE'99 Table of Contents

Sessions: [Keynote] [1A] [1B] [1C] [2A] [2B] [2C] [2E] [3A] [3B] [3C] [3E] [4A] [4B] [4C] [4E] [5A] [5B] [5C] [5E] [6A] [6B] [6C] [6E] [7A] [7B] [7E] [8A] [8B] [8C] [8E] [9A] [9B] [9C] [9D] [9E] [10A] [10B] [10C] [10D] [10E] [11B] [11C] [11D] [11E] [Posters]

Event Steering Board
Conference Organizing Committee
Program Topic Co-Chairs
Conference Committee -- Continued
Vendors Committee
Technical Program Committee
Reviewers
Welcome to DATE 1999
Best Paper Awards
Tutorials

Plenary -- Keynote Session

Embedded System Design -- The European Technology Driver

Moderator: R. Ernst, TU Braunschweig, D

Higher Product Complexity and Shorter Development Time - Continuous Challenge to Design and Test Environment [p. 2]
J. Junkkari

Automotive Electronics -- A Challenge for Systems Engineering [p. 4]
P. Thoma

Testing in Nanometer Technologies [p. 5]
T. Williams

Session 1A: Verification of Sequential Circuits

Moderators: H. Eveking, Darmstadt TU, D; C. Meinel, Trier U, D

Computing Timed Transition Relations for Sequential Cycle-Based Simulation [p. 8]
G. Cabodi, P. Camurati, C. Passerone, S. Quer

Symbolic Reachability Analysis of Large Finite State Machines using Don't Cares [p. 13]
Y. Hong, P. Beerel

Session 1B: Architectural Issues in Low Power Design

Moderators: G. De Micheli, Stanford U, USA; L. Benini, Bologna U, IT

FSMD Functional Partitioning for Low Power [p. 22]
E. Hwang, F. Vahid, Y. Hsu

A New Parameterizable Power Macro-Model for Datapath Components [p. 29]
G. Jochens, L. Kruse, E. Schmidt, W. Nebel

Session 1C: Design Reuse Repository and IP Architecture

Moderators: R. Seepold, FZI Karlsruhe, D; L. Claesen, IMEC/KU Leuven, B

An Efficient Reuse System for Digital Circuit Design [p. 38]
A. Reutter, W. Rosenstiel

An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]
M. Ikeda, T. Kondo, K. Nitta, K. Suguri, T. Yoshitome, T. Minami, J. Naganuma, T. Ogura

Session 2A: High Level Verification

Moderators: L. Claesen, IMEC/KU Leuven, B; L. Pierre, Provence U, F

Formal Verification of Word-Level Specifications [p. 52]
S. Höreth, R. Drechsler

Automatic Verification of Scheduling Results in High-Level Synthesis [p. 59]
H. Eveking, H. Hinrichsen, G. Ritter

Verifying Imprecisely Working Arithmetic Circuits [p. 65]
M. Huhn, K. Schneider, T. Kropf, G. Logothetis

Session 2B: System-Level Power Optimisation

Moderators: W. Nebel, Oldenburg U, D; E. Macii, Politecnico di Torino, IT

Battery-Powered Digital CMOS Design [p. 72]
M. Pedram, Q. Wu

Dynamic Power Management for Non-Stationary Service Requests [p. 77]
E. Chung, G. De Micheli, L. Benini, A. Bogliolo

On Reducing Transitions through Data Modifications [p. 82]
R. Murgai, M. Fujita

Session 2C: Reconfigurability and Other Issues in Embedded System Design

Moderators: D. Verkest, IMEC, B; P. van der Wolf, Philips Research, NL

Kernel Scheduling in Reconfigurable Computing [p. 90]
R. Maestre, R. Hermida, M. Fernandez, F. Kurdahi, N. Bagherzadeh, H. Singh

CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems [p. 97]
B. Dave

Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors [p. 105]
R. Leupers

Session 2E: Embedded Core Test Approaches

Moderators: Y. Zorian, LogicVision, USA; M. Lobetti Bodoni, Italtel, IT

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks [p. 112]
D. Nikolos, H. Vergos, T. Haniotakis, Y. Tsiatouhas

An Effective BIST Architecture for Fast Multiplier Cores [p. 117]
A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian

A CAD Framework for Generating Self-Checking Multipliers based On Residue Codes [p. 122]
I. Noufal, M. Nicolaidis

Session 3A: Use of Combinational Verification

Moderators: P. Camurati, Politecnico di Torino, IT; C. Meinel, Trier U, D

An Efficient Filter-based Approach for Combinational Verification [p. 132]
R. Mukherjee, J. Jain, K. Takayama, M. Fujita, J. Abraham, D. Fussell

Using Combinational Verification for Sequential Circuits [p. 138]
R, Ranjan, V. Singhal, F. Somenzi, R. Brayton

Combinational Equivalence Checking using Satisfiability and Recursive Learning [p. 145]
J. Marques-Silva, T. Glass

Formally Verified Redundancy Removal [p. 150]
S. Hendricx, L. Claesen

Session 3B: Gate Level Power Estimation and Optimisation

Moderators: M. Pedram, U Southern California, USA; G. Guardini, STMicroelectronics, IT

Logic Transformation for Low Power Synthesis [p. 158]
K. Kim, S. Kang, T. Hwang and C. Liu

Glitch Power Minimization by Gate Freezing [p. 163]
L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino, R. Scarsi

Spanning Tree Based State Encoding for Low Power Dissipation [p. 168]
W. Nöth, R. Kolla

Peak Power Estimation using Genetic Spot Optimization for Large VLSI Circuits [p. 175]
M. Hsiao

Session 3C: Special Session -- Virtual Socket Interface Alliance

Organizer and Chair: Ralf Seepold, FZI Karlsruhe, D

Virtual Socket Interface Alliance [p. 182]
R. Seepold

Speakers :

VSI Builds Momentum To Solve Design Reuse Imperative
L. Rosenberg

The VSI System-Level Perspective On The MIX and Match of Virtual Components
M. Genoe

Introduction To Virtual Component Interface
G. Matthew

Session 3E: Fault Diagnosis Techniques for Analogue Circuits

Moderators: J. L. Huertas, CNM Sevilla, ES; A. Ivanov, UBC Vancouver, CAN

A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester [p. 184]
E. Cota, L. Carro, M. Lubaszewski

Minimal Length Diagnostic Tests for Analog Circuits using Test History [p. 189]
A. V. Gomes, A. Chatterjee

Parametric Fault Diagnosis for Analog Systems using Functional Mapping [p. 195]
S. Cherubal, A. Chatterjee

Session 4A: Resource Sharing in Architectural Synthesis

Moderators: W. Rosenstiel, FZI Karlsruhe/Tuebingen U, D; P. Eles, Linköping U, SE

Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs [p. 202]
M. Kaul, R. Vemuri

Time Constrained Modulo Scheduling with Global Resource Sharing [p. 210]
C. Jäschke, F. Beckmann, R. Laur

Polynomial Methods for Allocating Complex Components [p. 217]
J. Smith, G. De Micheli

Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs [p. 223]
N. Mansouri, R. Vemuri

Session 4B: Mixed Signal Characterisation and Test

Moderators: A. Richardson, Lancaster U, UK; H. Kerkhoff, Twente UT, NL

A Digital Partial Built-In-Self-Test Structure for a High Performance Automatic Gain Control Circuit [p. 232]
A. Lechner, J. Ferguson, A. Richardson, B Hermes

Design, Characterization and Modeling of a CMOS Magnetic Field Sensor [p. 239]
L. Latorre, Y. Bertrand, P. Nouet, F. Pressecq, P. Hazard

Fast, Robust DC and Transient Fault Simulation for Nonlinear Analogue Circuits [p. 244]
Z. Yang, M. Zwolinski

On Analog Signature Analysis [p. 249]
F. Novak, B. Hvala, and S. Klavzar

Session 4C: System Design Methodologies: Modelling, Analysis, Refinement and Synthesis

Moderators: N. Zergainoh, TIMA, Grenoble, F; M. Kovac, TU Zagreb, CRO

The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems [p. 256]
A. Jantsch, A. Hemani, S. Kumar

MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis [p. 263]
R. Dick, N. Jha

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement [p. 271]
R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, I. Bolsens

Session 4E: High Level Test Synthesis

Moderators: Z. Peng, Linköping U, SE; B. Rouzeyre, LIRMM, F

Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs [p. 278]
J. Carletta, M. Nourani, C. Papachristou

Channel-Based Behavioral Test Synthesis for Improved Module Reachability [p. 283]
Y. Makris, A. Orailoglu

Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths [p. 289]
N. Nicolici, B. Al-Hashimi

Session 5A: High-Level System Simulation

Moderators: H. Fleurkens, Philips Research, NL; M. Pfaff, Linz U, A

A Retargetable, Ultra-Fast Instruction Set Simulator [p. 298]
J. Zhu, D. Gajski

High-Speed Software-based Platform for Embedded Software of a Single-Chip MPEG-2 Video Encoder LSI with HDTV Scalability [p. 303]
K. Ochiai, H. Iwasaki, J. Naganuma, M. Endo, T. Ogura

Fast Hardware-Software Co-Simulation using VHDL Models [p. 309]
B. Tabbara, M. Sgroi and A. Sangiovanni-Vincentelli, E. Filippi, L. Lavagno

Session 5B: Analogue Circuit Sizing and Synthesis

Moderators: G. Gielen, KU Leuven, B; F. Silveira, INESC, PT

Systematic Biasing of Negative Feedback Amplifiers [p. 318]
C. Verhoeven, A. van Staveren

Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints [p. 323]
R. Schwencker, J. Eckmueller, H. Graeb, K. Antreich

Hierarchical Constraint Transformation using Directed Interval Search for Analog System Synthesis [p. 328]
N. Dhanwada, A. Nunez-Aldana, R. Vemuri

Session 5C: VHDL-AMS and HDL Interoperability

Moderators: T. Kazmierski, Southampton U, UK; A. Vachoux, XEMICS S.A., CH

A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems [p. 338]
A. Doboli, R. Vemuri

Reasoning about VHDL and VHDL-AMS using Denotational Semantics [p. 346]
P. Breuer, N. Madrid, C. Kloos, J. Bowen, R. France, M. Petrie

A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstract State Machine [p. 353]
H. Sasaki

Session 5E: Transistor Level Test

Moderators: J Figueras, UP Catalunya, ES; C Landrault, LIRMM, F

Design for Testability Method for CML Digital Circuits [p. 360]
B. Antaki, Y. Savaria, N. Xiong, S. Adham

On the Design of Self-Checking Functional Units based on Shannon Circuits [p. 368]
M. Favalli, C. Metra

Parametric Built-In Self-Test of VLSI Systems [p. 376]
D. Niggemeyer, M. Rüffer

Session 6A: Hot Topic -- Hardware Synthesis From C/C++ Models

Organizer and Chair: Giovanni De Micheli, Stanford U, USA

Hardware Synthesis from C/C++ Models [p. 382]
G. De Micheli

C for System Level Design [p. 384]
G. Arnout

Hardware Synthesis from C/C++ [p. 387]
A. Ghosh, J. Kunkel, S. Liao

C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber" [p. 390]
K. Wakabayashi

Session 6B: Analogue Modelling and Simulation

Moderators: H. Graeb, TU Munich, D; C. Descleves, Dolphin Integration, F

Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's [p. 396]
J. Costa, L. Silveira, M. Chou

A Power Estimation Model for High-Speed CMOS A/D Converters [p. 401]
E. Lauwers, G. Gielen

An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis [p. 406]
A. Nunez-Aldana, R. Vemuri

An Accurate Error Control Mechanism for Simplification before Generation Algorithms [p. 412]
O. Guerra, J. Rodríguez-García, E. Roca, F. Fernández, A. Rodríguez-Vázquez

Session 6C: Hot Topic -- Chip Package Co-Design

Organizer and Chair : Ivo Bolsens, IMEC, B

Efficient Techniques for Modeling Chip-level Interconnect, Substrate and Package Parasitics [p. 418]
P. Feldman, S. Kapur, D. Long

Potentials of Chip-Package Co-Design for High-Speed Digital Applications [p. 423]
G. Tröster

A Single-Package Solution for Wireless Transceivers [p. 425]
P. Wambacq, S. Donnay, H. Ziad, M. Engels, H. De Man, I. Bolsens

Session 6E: Panel -- Scaling Towards Nanometer Technologies: Design for Test Challenges

Co-organized with IEEE Design and Test of Computers and MEDEA Program A-401
Organizer: Michael Nicolaidis, TIMA, F
Moderator : Yervant Zorian, LogicVision, USA

Scaling Deeper to Submicron: On-Line Testing to the Rescue [p. 432]
M. Nicolaidis, Y. Zorian

Panelists : Richard Ferrand, ST Microelectonics, F; Keith Baker, Philips, NL; Rob Roy, Intel, USA; Michael Nicolaidis, TIMA, F; Gunnar Carlsson, Ericsson, SE; Gunter Krampl, Siemens, D

Session 7A: Functional Verification

Moderators: E Villar, Cantabria U, ES; A Balboni, Italtel, IT

Functional Verification Methodology for Microprocessors using the Genesys Test-Program Generator -- Application to the X86 Microprocessors Family [p. 434]
L. Fournier, Y. Arbetman, M. Levinger

Symbolic Functional Vector Generation for VHDL Specifications [p. 442]
F. Ferrandi, F. Fummi, L. Gerli, D. Sciuto

Session 7B: Bit-Level Logic and Analogue Simulation

Moderators: P. Schwarz, FhG IIS/EAS Dresden, D; M. Koch, FH Stralsund, D

Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams [p. 448]
X. Tan, C. Shi

Cycle-based Simulation with Decision Diagrams [p. 454]
R. Ubar, J. Raik, A. Morawiec

Efficient Switching Activity Simulation under a Real Delay Model using a Bitparallel Approach [p. 459]
M. Bühler, M. Papesch, K. Kapp and U. Baitinger

Session 7E: Partial and Boundary Scan Test

Moderators: E. Aas, Trondheim U, NOR; T.W. Williams, Synopsys Inc., USA

Full Scan Fault Coverage with Partial Scan [p. 468]
X. Lin, I. Pomeranz, S. Reddy

At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks [p. 473]
J. Shin, H. Kim, S. Kang

Session 8A: New Languages for System Specification and Design

Moderators: C. Delgado-Kloos, U Carlos III de Madrid, ES; W. Fornaciari, Politecnico di Milano, IT

OpenJ: An Extensible System Level Design Language [p. 480]
J. Zhu, D. Gajski

EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability [p. 485]
A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, A. Nicolau

Data Type Analysis for Hardware Synthesis from Object-Oriented Models [p. 491]
M. Radetzki, A. Stammermann, W. Putzke-Röming, W. Nebel

Session 8B: Circuit Analysis and Design

Moderator: A. Trullemans-Anckaert, UCL, B

How to use Knowledge in an Analysis Process [p. 498]
H. Holzheuer

Digital MOS Circuit Partitioning with Symbolic Modeling [p. 503]
L. Ribas, J. Carrabina

High Speed GaAs Subsystem Design using Feed through Logic [p. 509]
J. Montiel-Nelson, V. de Armas, R. Sarmiento, A. Núñez, S. Nooshabadi

Session 8C: Logic Synthesis

Moderators: R. Drechsler, Freiburg U, D; M. Berkelaar, Eindhoven UT, NL

Integrating Symbolic Techniques in ATPG-based Sequential Logic Optimization [p. 516]
E. San Millán, L. Entrena, J. Espejo, S. Chiusano, F. Corno

An Algorithm for Face-Constrained Encoding of Symbols using Minimum Code Length [p. 521]
M. Martínez, M. Avedillo, J. Quintana, J. Huertas

Algorithms for Solving Boolean Satisfiability in Combinational Circuits [p. 526]
L. Guerra e Silva, L. Silveira, J. Marques-Silva

Wavefront Technology Mapping [p. 531]
L. Stok, M. Iyer, A. Sullivan

Session 8E: IDDX Testing and Defect Modelling

Moderators: K. Baker, Philips ED&T, NL; J. Segura, Illes Balears U, ES

On-Chip Transient Current Monitor for Testing of Low-Voltage CMOS IC [p. 538]
V. Stopjaková, H. Manhaeve, M. Sidiropulos

Exploring the Combination of IDDQ and iDDt Testing: Energy Testing [p. 543]
J. Rius and J. Figueras

Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip using HDL [p. 549]
M. Santos, J. Teixeira

Session 9A: HW/SW Interface Synthesis and Partitioning

Moderators: K. Kuchcinski, Linköping U, SE; J. Calvez, IRESTE, F

Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints [p. 556]
S. Vercauteren, D. Verkest, J. Van Der Steen

Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification [p. 562]
M. O'Nils, A. Jantsch

Codex-dp: Co-Design of Communicating Systems using Dynamic Programming [p. 568]
J. Chang, M. Pedram

Session 9B: Physical Design Issues

Moderator: F Johannes, TU Munich, D

Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts [p. 576]
A. Toulouse, D. Bernard, C. Landrault, P. Nouet

Post-Placement Residual-Overlap Removal with Minimal Movement [p. 581]
S. Nag, K. Chaudhary

Iterative Improvement based Multi-Way Netlist Partitioning for FPGAs [p. 587]
H. Krupnova, G. Saucier

Session 9C: Reliability and Symmetry in Architectural Synthesis

Moderators: F. Kurdahi, UC Irvine, USA; R. Hermida, U Complutense Madrid, ES

Self Recovering Controller and Datapath Codesign [p. 596]
S. Hamilton, A. Orailoglu, A. Hertwig

Identification and Exploitation of Symmetries in DSP Algorithms [p. 602]
C. van Eijk, E. Jacobs, B. Mesman, and A. Timmer

Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation [p. 609]
L. dos Santos, J. Jess

Session 9D: Panel -- Single Chip or Hybrid System Integration ?

Organizer and Moderator : Ivo Bolsens, IMEC, B

Single Chip or Hybrid System Integration ? [p. 616]
I. Bolsens

Panelists: Wojtek Maly, CMU, USA; Ludo Deferm, IMEC, B; Jo Borel, ST, F; Harry Veendrick, Philips, NL

Session 9E: Testing Regular Structures and Delay Faults

Moderators: L. Bouzaida, STMicroelectronics, F; D. Bhatacharya, Texas Instruments, USA

Testing the Configurable Interconnect/Logic Interface of SRAM-based FPGA's [p. 618]
M. Renovell, J. Portal, J. Figueras, Y. Zorian

Industrial Evaluation of DRAM Tests [p. 623]
A. van de Goor, J. de Neef

ATPG Tools for Delay Faults at the Functional Level [p. 631]
M. Michael, S. Tragoudas

Session 10A: Retiming

Moderators: M. Berkelaar, Eindhoven UT, NL; R. Drechsler, Freiburg U, D

Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence [p. 638]
P. Kalla, M. Ciesielski

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits [p. 643]
M. Papaefthymiou, E. Friedman, X. Liu

Retiming Sequential Circuits with Multiple Register Classes [p. 650]
K. Eckl, C. Legl

Session 10B: Modelling of Interconnects

Moderator: T Akino, Kinki U, JP

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs [p. 658]
L. Ye, F. Chang, P. Feldmann, R. Chadha, N. Nagaraj, F. Cano

Coupled Noise Estimation for Distributed RC Interconnect Model [p. 664]
J. Wang, Q. Yu, E. Kuh

Projective Convolution: RLC Model-Order Reduction using the Impulse Response [p. 669]
B. Sheehan

Session 10C: Design Reuse Methodologies for Virtual Components and IP

Moderators: R. Seepold, FZI Karlsruhe, D; J Agaesse, Thomson-CSF, F

The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs [p. 676]
M. Jacome, H. Peixoto, A. Royo, J. Lopez

Specification and Validation of Distributed IP-based Designs with JavaCAD [p. 684]
M. Dalpasso, A. Bogliolo, L. Benini

Object-Oriented Reuse Methodology for VHDL [p. 689]
C. Barna, W. Rosenstiel

Session 10D: Embedded Tutorial -- Multi-language System Design

Moderator: Ahmed Amine Jerraya, TIMA, F

Multi-language System Design [p. 696]
A. Jerraya, R. Ernst

Contributors: Rolf Ernst, TU Braunschweig, D; Ahmed Amine Jerraya, TIMA, F

Session 10E: RAM BIST

Moderators: W. Daehn, Siemens AG, D; G. Carlsson, Ericsson, SE

Symmetric Transparent BIST for RAMs [p. 702]
S. Hellebrand, H. Wunderlich, V. Yarmolik

On Programmable Memory Built-in Self Test Architectures [p. 708]
K. Zarrineh, S. Upadhyaya

A Physical Design Tool for Built-In Self-Repairable Static RAMS [p. 714]
K. Chakraborty, A. Gupta, M. Bhattacharya, S. Kulkarni, P. Mazumder

Session 11B: Panel -- Java, VHDL-AMS, Ada or C for System Level Specifications?

Organizer and Chair : Wolfgang Nebel, Oldenburg U, D
Co-Organizer: Giulio Gorla, Italtel, IT

Java, VHDL-AMS, Ada or C for System Level Specifications? [p. 720]
W. Nebel

Case Study: System Model of Crane and Embedded Control [p. 721]
E. Moser, W. Nebel

Panelists: Tom Kazmierski, U Southampton, UK; Eugenio Villar, U Cantabria, ES; Daniel D. Gajski, UC Irvine, USA; Eduard Moser, Bosch, D; Judith Benzakki, U Evry Val d'Essonne, F

Session 11C: Hot Topic -- IP And Reuse

Organizer and Chair : Wolfgang Rosenstiel, FZI Karlsruhe, D

Virtual Components Application and Customization [p. 726]
J. Agaësse, B. Laurent

Design Methodology for IP Providers [p. 728]
J. Haase

Speakers: R. Seepold, FZI Karlsruhe, D; R. Haase, SICAN, D; J.F. Agaësse, Thomson-CSF, F

Session 11D: Special Session -- Large European Programs in Microelectronic System and Circuit Design

Organizers: D.Borrione, TIMA, F; P. Dewilde, TU Delft, NL
Chair: I. Bolsens, IMEC, B

Large European Programs in Microelectronic System and Circuit Design [p. 734]
P. Dewilde

Speakers:

MEDEA's Contribution to the Strength of European Design and CAD
A. Sauer

Electronic Systems Design in the IST Program
H. Forster

ITEA -- Information Technology and European Advancement
E. Daclin

Session 11E: Sequential Circuit Test Generation

Moderators: E. Gramatova, Slovak Academy of Sciences, SLK; A. Benso, Politecnico di Torino, IT

Sequential Circuit Test Generation using Decision Diagram Models [p. 736]
J. Raik, R. Ubar

Illegal State Space Identification for Sequential Circuit Test Generation [p. 741]
M. Konijnenburg, J. van der Linden, A. van de Goor

FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy [p. 747]
Y. Santoso, M. Merten, E. Rudnick, M. Abramovici

Posters

Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms [p. 754]
F. Corno, M. Sonza Reorda, G. Squillero

Interval Diagram Techniques for Symbolic Model Checking of Petri Nets [p. 756]
K. Strehl, L. Thiele

Variable Reordering for Shared Binary Decision Diagrams using Output Probabilities [p. 758]
M. Thornton, J. Williams, R. Drechsler, N. Drechsler

Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering [p. 760]
C. Meinel, C. Stangier

Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems [p. 762]
W. Fornaciari, D. Sciuto, C. Silvano

Emulation of a Fast Reactive Embedded System using a Real Time Operating System [p. 764]
K. Weiß, T. Steckstor, W. Rosenstiel

The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach [p. 766]
J. Maestro, D. Mozos, R. Hermida

Codesign of Embedded Systems based on Java and Reconfigurable Hardware Components [p. 768]
J. Fleischmann, K. Buchenrieder, R. Kress

ADOLT -- An ADaptable On-Line Testing Scheme for VLSI Circuits [p. 770]
A. Maamar, G. Russell

Integrated Resource Assignment and Scheduling of Task Graphs using Finite Domain Constraints [p. 772]
K. Kuchcinski

A Method of Distributed Controller Design for RTL Circuits [p. 774]
C. Papachristou, Y. Alzazeri

OTA Amplifiers Designed on Digital Sea-of-Transistors Array [p. 776]
J. Choi and S. Bampi

A DAG-Based Design Approach for Reconfigurable VLIW Processors [p. 778]
C. Alippi, W. Fornaciari, L. Pozzi, M. Sami

A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis [p. 780]
J. Wu, E. Rudnick, G. Greenstein

An Object-Based Executable Model for Simulation of Real-Time HW/SW Systems [p. 782]
O. Pasquier, J. Calvez

An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic Systems [p. 784]
S. Scherber, C. Müller-Schloer

Software Bit-Slicing: A Technique for Improving Simulation Performance [p. 786]
P. Maurer, W. Schilp

Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI [p. 788]
F. Martinolle, C. Dawson, D. Corlette, M. Floyd

Experiences with Modeling of Analog and Mixed A/D Systems based on PWL Technique [p. 790]
J. Dabrowksi, A. Pulka

A One-Bit Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection [p. 792]
I. Rayane, J. Velasco-Medina, M. Nicolaidis