DATE'99 Session Index

Session 1A: Verification of Sequential Circuits
Improved techniques for the approximate and exact reachability analysis of sequential systems are presented considering don't cares and long counting sequences.

Session 1B: Architectural Issues in Low Power Design
Design exploration at the architectural level is key for achieving power efficient systems. The first paper of this session presents a new partitioning technique for FSHD that enables efficient power management. The second paper proposes a new parameterizable macromodel for behavioural datapath components.

Session 1C: Design Reuse Repository and IP Architecture
The first paper presents a reuse system that has been implemented and is used for digital circuit design. It supports 'design for reuse' and 'reuse of design' customised for intra-company reuse. The second paper documents a new architecture of a video encoder with a scalability for HDTV.

Session 2A: High Level Verification
Novel high level verification techniques for dedicated datapath word-level decision diagrams, imprecise arithmetic, as well as for automatic scheduling and model checking are presented.

Session 2B: System-Level Power Optimisation
Power optimisation at the system level is recognised as an increasingly important task. The first paper in this session introduces a new way of looking at the problem by considering battery life in the cost function used for the optimisation. The second paper deals with OS-based power management of non stationary workloads. Finally, the third paper proposes new encoding schemes for reducing interface power.

Session 2C: Reconfigurability and Other Issues in Embedded System Design
This session focuses on the challenges and opportunities that reconfigurable platforms offer for co-design and emulation of embedded systems. Further issues addressed are code generation for embedded VLIW processors and the role of high-level estimations to decide on resource sharing.

Session 2E: Embedded Core Test Approaches
This session brings a number of solutions for testing embedded cores. From delay fault testing to functional testing of cores used in today's system-on-chip.

Session 3A: Use of Combinational Verification
Core techniques of combinational verification may be combined or can be applied to sequential verification problems.

Session 3B: Gate Level Power Estimation and Optimisation
This session addresses logic synthesis for low power issues. The first paper introduces a set of logic transformations that enable power reductions of gate-level netlists. The second paper proposes a new approach for post layout glitch power minimisation. A novel state encoding algorithm is presented in the third contribution. Finally, the fourth paper deals with peak power estimation methods.

Session 3C: Special Session -- Virtual Socket Interface Alliance
The first presentation will present the technical objectives and background of the work of VSI Alliance. The driving factors and actual achievements will be shown in the context of actual research, development and standardization trends. The second talk is focused on Virtual prototyping of complete mixed hardware (HW)-software (SW) systems that require well-defined multi-level description of the VC interfaces. The third presentation will introduce the VSI Virtual Component Interface, and show how this can map the transactions used in System Level Design onto a range of on-chip bus implementations for different cost/performance tradeoffs.

Session 3E: Fault Diagnosis Techniques for Analogue Circuits
This session presents new techniques to diagnose faults in analogue circuits. The first method consists of using an adaptive tester that learns a reference behaviour in a first step. The second method uses information coming from previous samples to resolve ambiguities. The last method consists of using a non-linear regression model using prior circuit simulations.

Session 4A: Resource Sharing in Architectural Synthesis
This session addresses different resource sharing approaches. Whereas the first paper concentrates on temporal partitioning of reconfigurable processors, the second paper discusses resource sharing among multiple processes, while the third one deals with optimising the allocation of complex components. The last paper investigates post synthesis formal verification of RTL designs generated by high level synthesis.

Session 4B: Mixed Signal Characterisation and Test
Problems relating to characterisation and test of complex mixed signal systems will be addressed in this session. The first paper will present a digital partial BIST solution for an AGC that aims to reduce test time and complexity. The second paper will look at characterisation and modelling issues in a new magnetic field sensor and the final two short papers will address the problems of analogue simulation and test response handling.

Sessions4C: System Design Methodologies: Modelling, Analysis, Refinement and Synthesis
The first paper presents main concepts in the electronic system design such as: modelling, analysis and synthesis. The second paper addresses a system synthesis algorithm which partitions and schedules embedded systems specifications to intellectual property cores in an integrated circuit. Finally, the third paper proposes a refinement methodology to move the DSP functions from a floating point to a fixed point representation in the case of implementing these functions in hardware (ASIC).

Session 4E: High Level Test Synthesis
This session deals with high-level synthesis of testable designs. The first paper presents a technique to test datapath-controller pairs in an integrated fashion. The second paper addresses the issues of module reachability for test purpose during high-level synthesis. The last paper describes a BIST insertion technique used in a partial intrusion BIST environment.

Session 5A: High-Level System Simulation
The design of a complex system (like that of an MPEG encoder) needs improved simulation, C-based simulation and VHDL-based HW/SW-cosimulation are very promising methods. Three posters present additional approaches for modelling and simulation of complex systems.

Session 5B: Analogue Circuit Sizing and Synthesis
New developments in analogue circuit sizing and synthesis are discussed, both at the level of basic circuits and higher levels. First, a systematic biasing method is presented. Next, an automatic sizing approach that considers structural constraints. Finally, constraint transformation at higher levels is described.

Session 5C: VHDL-AMS and HDL Interoperability
The papers in this session cover various aspects of analogue and mixed-signal modelling using VHDL and VHDL-AMS as well as mixed-language hardware description issues, VHDL-Verilog interoperability and formal semantics.

Session 5E: Transistor Level Test
Transistor level DFT for Current Mode Logic is addressed in the first paper. The next paper deals with pass-transistor implementations of self-checking circuits. The last paper presents a new approach for parametric on-chip testing.

Session 6A: Hot Topic -- Hardware Synthesis From C/C++ Models
Designers often use programming languages to model hardware, because of the ease of simulating the high-level behaviour (possibly in conjunction with software), of migrating software code to hardware and of using legacy models. Hardware synthesis from programming language models is challenging, due to the lack of an underlying hardware semantics. Nevertheless, synthesis from C/C++ subsets has become reality, and this session wil present current approaches, their advantages and limitations.

Session 6B: Analogue Modelling and Simulation
The first paper deals with substrate coupling modelling. The second paper presents a new model for high-level performance estimation of converters. The following two papers present qualitative performance modelling for simulation oriented synthesis and efficient symbolic performance modelling.

Session 6C: Hot Topic -- Chip Package Co-Design
Traditionally there has been very limited interaction between IC design and packaging design. It is expected however, that for some applications the increasingly aggresive system performance requirements will necessitate a concurrent design of ICs and packages in the future. For high-performant systems, chip-package co-design means the optimal distribution of the routing between on-chip and off-chip interconnections. Also, future telecom products will benefit from the availiability of these integrated passives to achieve lower cost, better performance and faster development time. Finally, the modeling and simulation problems have to be addressed. An overview of existing solution techniques, such as efficient extraction algorithms and reduced-order modeling methods will be presented. Current challenges and open problems will also be discussed.

Session 6E: Panel -- Scaling Towards Nanometer Technologies: Design for Test Challenges
The continuous scaling in microelectronics results in numerous challenges that test technology should overcome, such as reduced noise margins; reduced accessibility; increased inadequacy between IC generations and Automatic Test Equipment, and complex defect behavior, making performance and other spurious faults predominant. The panel will discuss the relevance of these challenges to nanometer technologies and try to identify potential solutions for them.

Session 7A: Functional Verification
Functional correctness assessment represents one of the primary and most time-consuming tasks of the complete design process. In this session, two different approaches to the problem are presented. The first one describes a rigorous methodology for microprocessor design verification. The second presents a new approach for functional vector generation based on a precise behavioural error model and a controllability metric on VHDL code coverage evaluation.

Session 7B: Bit-Level Logic and Analogue Simulation
Decision Diagrams -- related to the well-known BDDs -- offer a new method for improved simulation efficiency both in the analogue and digital area. The symbolic calculation of the transfer function of linear systems gives additional insight into the main functionality of analogue circuits. Precise delay models (covering hazards and glitches) and effective bitparallel evaluation is the basis of switching activity simulation especially as applied in low-power design.

Session 7E: Partial and Boundary Scan Test
An original 3-phase procedure based on structural and functional analysis for partial scan is presented, together with a novel solution to execute dynamic interconnect test at the board level.

Session 8A: New Languages for System Specification and Design
This session presents new languages for heterogeneous system specifications, to support design space exploration and an optimisation strategy for synthesis of data types from high level specifications.

Session 8B: Circuit Analysis and Design
The first paper presents a knowledge enriched approach for signal integrity analysis. Automatic recognition and modelling of logic gates out of a switch-level network is the topic of the second paper. Finally, the design of fast arithmetic circuits using GaAs based Feed through Logic is presented.

Session 8C: Logic Synthesis
This session contains four papers which advance the state-of-the-art in various basic logic synthesis techniques.

Session 8E: IDDX Testing and Defect Modelling
Defect modelling and defect detection are very important for test. This session explores traditional IDDQ testing plus IDDT testing, where T = transient. In addition, defect-oriented fault simulation is presented.

Session 9A: HW/SW Interface Synthesis and Partitioning
The papers presented in this session concentrate on interface synthesis and partitioning of HW/SW embedded systems. The first paper combines software synthesis and automatic HW/SW interface generation to meet hard real-time constraints for digital communication systems. Generation of the software part of the HW/SW interface is the topic of the second paper. The third paper discusses the use of dynamic programming for HW/SW partitioning and mapping of communicating processes.

Session 9B: Physical Design Issues
In this session three different aspects of physical design are discussed. The first paper presents a set of analytical formulations for 3D modelling of interlayer capacitances. In the second paper the sequence-pair approach is applied to systematically remove overlaps between placed objects. An improved iterative partitioning method for FPGAs is proposed in the third paper.

Session 9C: Reliability and Symmetry in Architectural Synthesis
The first paper discusses the synthesis of reliable self recovering architectures while avoiding redundancies in the controller. The last two papers exploit symmetries in architectural synthesis in order to speed -up the design tools.

Session 9D: Panel -- Single Chip or Hybrid System Integration ?
If we continue to increase the complexity of ICs at the same pace as we did from 1960 onwards, this complexity will have reached half a billion transistors per chip, within a decade from now. And the clock period is `expected' to be well below the one nanosecond. This panel will discuss future trends of cost, power, speed, reliability and signal integrity. If we don't believe these excessive numbers, design styles and methods as well as integration technology need to be changed to cope with the complexity and performance of future embedded systems This panel will discuss the consequences for deep-submicron IC design and possible way outs for the roadblocks.

Session 9E: Testing Regular Structures and Delay Faults
This session includes presentations on minimum length test patterns for SRAM-based FPGA structures, industrial evaluation of a large number of memory test algorithms on DRAM circuits, and functional ATPG tools for delay faults.

Session 10A: Retiming
This session presents three papers which extend the usability of retiming in a synthesis environment.

Session 10B: Modelling of Interconnects
In deep submicron design the modelling of interconnect becomes increasingly important. The first paper describes technologies for the modelling and analysis of parasitic coupling effects for large VLSI design. The other two papers present different approaches to modelling and reduction of interconnect networks.

Session 10C: Design Reuse Methodologies for Virtual Components and IP
The first paper presents a design space layer that is introduced to support both IP-based design methodologies and traditional design methodologies. The second paper introduces a Java-CAD framework that uses remote components and that supports secure Internet protocol for a smooth transition between component evaluation. The third paper presents a methodology to decrease re-design effort . This methodology is implemented on an already existing reuse management system.

Session 10D: Embedded Tutorial -- Multi-language System Design
The design of large systems, like a mobile telecommunication terminal or the electronic parts of an airplane or a car, may require the participation of several groups belonging to different companies and using different design methods, languages and tools. The concept of multi-language specification aims at coordinating different cultures through the unification of the languages, formalism, and notations. There are two main approaches for multilanguage design: the compositional approach and the cosimulation-based approach. The compositional approach aims at integrating the partial specification of sub-systems into a unified representation which is used for the verification and design of the global behavior. The cosimulation-based approach consists in interconnecting the design environments associated to each of the partial specifications. Compared with the deep specification integration accomplished by the compositional approaches, cosimulation is an engineering solution to multilanguage design that performs just a shallow integration of the partial specifications. This session discusses the key issues for multilanguage system design.

Session 10E: RAM BIST
The first two papers address built-in self-test of Random Access Memories. Symmetric transparent BIST is presented as a self-test method that does not destroy the content of the RAM. The second paper presents architectural differences of BIST engines for RAMs. The authors of the third paper discuss self repair of RAMs and the implications on yield.

Session 11B: Panel -- Java, VHDL-AMS, Ada or C for System Level Specifications?
This technical panel discussion compares and discusses the suitability of new and established languages for creating executable specifications of heterogeneous embedded systems. The comparison is made by champions of the languages JAVA, VHDL-AMS, ADA and C based on a common example, a portal crane. In particular the panel focuses on issues like modeling efficiency in different domains, execution performance and reusability.

Session 11C: Hot Topic -- IP And Reuse
The session will present different views on the same hot topic : IP and Reuse from the perspective of the IP provider and the IP user. Discussing and presenting each viewpoint, while the topic will be introduced by the state of the art presentation to guide participants into the reuse domain. At the end, a panel discussion is planned to invite the attendees to actively participate in the discussion by asking burning questions to the presentors.

Session 11D: Special Session -- Large European Programs in Microelectronic System and Circuit Design
Very large European programs in Microelectronic System and Circuit Design are presently under way or being designed. The scope and breadth of these programs is very large, with many companies and research groups participating. The speakers at this special session are executives who are primarily responsible for these programs. They present achievements of ongoing programs and future plans of continuing and starting programs. The presentations are followed by a discussion on the method and the principles.

Session 11E: Sequential Circuit Test Generation
The first paper presents a novel approach to testing sequential circuits by using multi-level decision diagrams. The second paper presents an ATPG system which focuses on discovering the illegal state space. The last contribution introduces a new testing strategy based on a frozen clock strategy which temporarily suspends the sequential behaviour of the circuit.

Posters