DATE'99 Abstracts

Plenary -- Keynote Session

Moderator: R. Ernst, TU Braunschweig, D

Higher Product Complexity and Shorter Development Time - Continuous Challenge to Design and Test Environment [p. 2]

J. Junkkari

Digital technologies enable more functionality and new attractive products at faster pace. What are the challenges faced in the development? How must the processes change? How must the tools change? How must the businesses change? What are the strategic questions to be answered?

Automotive Electronics -- A Challenge for Systems Engineering [p. 4]

P. Thoma

Increasing demand for dynamically controlled safety features, driving comfort and operational convenience in upper class cars require an intensive use of ECUs (electronic control units) including software. A network of up to 70 ECUs which are communicating via busses is mandatory for the required functionality. On the one hand, complexity of ECUs is rapidly increasing and time to market is decreasing. On the other hand, automotive electronics is developed together with many suppliers under control of the OEMs. Furthermore, 30% of the value added in automotive is up to electronics. Thus, from a technical, an administrative and from a business point of view the car manufactures have a vital interest to improve and shorten the software development process for ECUs together with all partners involved. As a consequence, a general objective is to improve the ECU development process based on standards. Besides OSEK as an already accepted standard for ECU software operating systems in Germany, the OEMs are also interested in standards for bus systems or for model exchange formats, to mention just a few. In addition, an improved ECU design process covers system analysis, system specification, system design, automatic code generation, an integration of ECUs and the corresponding software in a real environment as well as calibration and after sales services. A special topic is the independence of an ECU hardware architecture development and the corresponding function development. Another highlight is adding surplus value with respect to functionality by an intelligent combining of already existing ones. This presentation gives an overview about the current situation in automotive electronics design, presents a new design process and discusses the challenges.

Testing in Nanometer Technologies [p. 5]

T. Williams

The last 25 years have been a very exciting time for the people involved in testing. As an industry we had a very difficult time generating tests for boards which had only 1000 logic gates on them with packages which had only a few logic gates per module. Because of these difficulties a number of people started to look for different approaches to testing. It was clear to many that automatic test generation for sequential networks could not keep up with the rate of increasing network size. This resulted in many changes in the way designs were done. This increase in gate count resulted in the development of the area of Design for Testability. Test in these 25 years was driven by the increase in gate count coupled with the inability of automatic sequential test generation to keep pace.

Session 1A: Verification of Sequential Circuits

Improved techniques for the approximate and exact reachability analysis of sequential systems are presented considering don't cares and long counting sequences.

Computing Timed Transition Relations for Sequential Cycle-Based Simulation [p. 8]

G. Cabodi, P. Camurati, C. Passerone, S. Quer

In this paper we address the problem of computing silent paths in an Finite State Machine (FSM). These paths are characterized by no observable activity under constant inputs, and can be used for a variety of applications, from verification, to synthesis, to simulation.
First, we describe a new approach to compute the Timed Transition Relation of an FSM. Then, we concentrate on applying the methodology to simulation of reactive behaviors. In this field, we automatically extract a BDD{based behavioral model from the RT or Gate Level description. The behavioral model is able to "jump" in time and to avoid the simulation of internal events. Finally, we discuss a set of promising experimental results in a simulation environment under the Ptolemy simulator.

Symbolic Reachability Analysis of Large Finite State Machines using Don't Cares [p. 13]

Y. Hong, P. Beerel

Reachability analysis of finite state machines is essential to many computer-aided design applications. We present new techniques to improve both approximate and exact reachability analysis using don't cares. First, we propose an iterative approximate reachability analysis technique in which don't care sets derived from previous iterations are used in subsequent iterations for better approximation. Second, we propose new techniques to use the final approximation to enhance the capability and efficiency of exact reachability analysis. Experimental results show that the new techniques can improve reachability analysis significantly.

Session 1B: Architectural Issues in Low Power Design

Design exploration at the architectural level is key for achieving power efficient systems. The first paper of this session presents a new partitioning technique for FSHD that enables efficient power management. The second paper proposes a new parameterizable macromodel for behavioural datapath components.

FSMD Functional Partitioning for Low Power [p. 22]

E. Hwang, F. Vahid, Y. Hsu

Previous work has shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques focus on shutting down only portions of the controller or the datapath of a single custom hardware processor. We propose a higher level shutdown technique that considers both the controller and datapath simultaneously; in particular, we partition a processor into multiple simpler mutually-exclusive communicating processors, and then shut down the inactive processors (i.e., the inactive controller/datapath pairs). Power reduction is accomplished because only one smaller processor is active at a time. In addition to power reduction, functional partitioning also provides solutions to a variety of synthesis problems and does not require the modification of the synthesis tool. We present results showing that this FSMD functional partitioning technique can reduce power, on average, 42% over unoptimized systems.

A New Parameterizable Power Macro-Model for Datapath Components [p. 29]

G. Jochens, L. Kruse, E. Schmidt, W. Nebel

We propose a novel power macro-model which is based on the Hamming-distance of two consecutive input vectors and additional information on the module structure. The model is parameterizable in terms of input bit-widths and can be applied to a wide variety of datapath components. The good trade-off between estimation accuracy, model complexity and flexibility makes the model attractive for power analysis and optimization tasks on a high level of abstraction. Furthermore, a new approach is presented, that allows to calculate the average Hamming-distance distribution of an input data stream. It will be demonstrated, that the application of Hamming-distance distributions, instead of only average values, improves the estimation accuracy for a number of typical DSP-modules and data streams.

Session 1C: Design Reuse Repository and IP Architecture

The first paper presents a reuse system that has been implemented and is used for digital circuit design. It supports 'design for reuse' and 'reuse of design' customised for intra-company reuse. The second paper documents a new architecture of a video encoder with a scalability for HDTV.

An Efficient Reuse System for Digital Circuit Design [p. 38]

A. Reutter, W. Rosenstiel

In this paper a complete reuse system for digital circuit design is presented. Thereby "design for reuse" and "design by reuse" aspects are considered. In particular a repository for IPs with special emphasis on classification and selection, web integration and IP protection is developed. By practising intra-company reuse with our system the efficiency and performance of reuse is demonstrated.

An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture [p. 44]

M. Ikeda, T. Kondo, K. Nitta, K. Suguri, T. Yoshitome, T. Minami, J. Naganuma, T. Ogura

This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-um four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

Session 2A: High Level Verification

Novel high level verification techniques for dedicated datapath word-level decision diagrams, imprecise arithmetic, as well as for automatic scheduling and model checking are presented.

Formal Verification of Word-Level Specifications [p. 52]

S. Höreth, R. Drechsler

Formal verification has become one of the most important steps in circuit design. In this context the verification of high-level Hardware Description Languages (HDLs), like VHDL, gets increasingly important. In this paper we present a complete set of datapath operations that can be formally verified based on Word-Level Decision Diagrams (WLDDs). Our techniques allow a direct translation of HDL constructs to WLDDs. We present new algorithms for WLDDs for modulo operation and division. These operations turn out to be the core of our efficient verification procedure. Furthermore, we prove upper bounds on the representation size of WLDDs guaranteeing effectiveness of the algorithms. Our verification tool is totally automatic and experimental results are given to demonstrate the efficiency of our approach.

Automatic Verification of Scheduling Results in High-Level Synthesis [p. 59]

H. Eveking, H. Hinrichsen, G. Ritter

A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented. The technique is applicable to the results of advanced scheduling methods like AFAP and DLS, which work on cyclic control flows, as well as to pipelined designs.

Verifying Imprecisely Working Arithmetic Circuits [p. 65]

M. Huhn, K. Schneider, T. Kropf, G. Logothetis

If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between the mathematical specification based on real numbers and the corresponding hardware realization. Instead, the number representation has to be taken into account in that certain error bounds have to be verified. For this reason, we propose formal methods to guide the complete design flow of these circuits from the highest abstraction level down to the register-transfer level with formal verification techniques that are appropriate for the corresponding level. Hence, our method is hybrid in the sense that it combines different state-of-the-art verification techniques. Using our method, we establish a more detailed notion of correctness that considers beneath the control and data flow also the preciseness of the numeric calculations. We illustrate the method with the discrete cosine transform as a real-world example.

Session 2B: System-Level Power Optimisation

Power optimisation at the system level is recognised as an increasingly important task. The first paper in this session introduces a new way of looking at the problem by considering battery life in the cost function used for the optimisation. The second paper deals with OS-based power management of non stationary workloads. Finally, the third paper proposes new encoding schemes for reducing interface power.

Battery-Powered Digital CMOS Design [p. 72]

M. Pedram, Q. Wu

In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In contrast to previous work, we adopt an integrated model of the VLSI circuit and the battery sub-system that powers it. We show that accounting for the dependence of battery capacity on the average discharge current changes shape of the energy-delay trade-off curve and hence the value of the operating voltage that results in the optimum energy-delay product for the target circuit. Analytical derivations as well as experimental results demonstrate the importance of correct modeling of the battery-hardware system as a whole and provide a more accurate basis for comparing various low power optimization methodologies and techniques targeted toward battery-powered electronics.

Dynamic Power Management for Non-Stationary Service Requests [p. 77]

E. Chung, G. De Micheli, L. Benini, A. Bogliolo

Dynamic Power Management is a design methodology aiming at reducing power consumption of electronic systems, by performing selective shutdown of the idle system resources. The effectiveness of a power management scheme depends critically on an accurate modeling of the environment, and on the computation of the control policy. This paper presents two methods for characterizing non-stationary service requests by means of a prediction scheme based on sliding windows. Moreover, it describes how control policies for non-stationary models can be derived.

On Reducing Transitions through Data Modifications [p. 82]

R. Murgai, M. Fujita

Since busses take up significant fraction of chip-area, the bus capacitances are often considerable, and the bus power may account for as much as 40% of the total power consumed on the chip [5]. In applications where the integrity of data is not very important, data may be changed by 3 to 5% without losing too much information. One such application is that of a binary-encoded image, in which case the human eye cannot perceive the small change. However, these small changes can significantly reduce the number of transitions on the data bus and thus the power/energy consumed. We address the following problem: Given a sequence of n k-bit data words and an error-tolerance e% (i.e., at most e% of the data bits are permitted to change), select the bits to be modified so that the total number of transitions is minimized. We show that a greedy strategy is not always optimum. We propose a linear-time dynamic programming based algorithm that generates an optimum solution to this problem. The experimental results for randomly generated data with a uniform distribution indicate that by changing e% data bits, the transitions can be reduced, on average, by 4e%.

Session 2C: Reconfigurability and Other Issues in Embedded System Design

This session focuses on the challenges and opportunities that reconfigurable platforms offer for co-design and emulation of embedded systems. Further issues addressed are code generation for embedded VLIW processors and the role of high-level estimations to decide on resource sharing.

Kernel Scheduling in Reconfigurable Computing [p. 90]

R. Maestre, R. Hermida, M. Fernandez, F. Kurdahi, N. Bagherzadeh, H. Singh

Reconfigurable computing is a flexible way of facing with a single device a wide range of applications with a good level of performance. This area of computing involves different issues and concepts when compared with conventional computing systems. One of these concepts is context loading. The context refers to the coded configuration information to implement a particular circuit behavior. An important problem for reconfigurable computing is the scheduling of a group of kernels (sub-tasks) that constitute a complex application for minimum execution time. In this paper, we show how the different execution orders for these sub-tasks may result in varying levels of performance. We formulate an analytical approach and present a solution for this new problem through this work.

CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems [p. 97]

B. Dave

Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-time reconfigurable hardware components such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). In this paper, we address the problem of hardware/ software co-synthesis of dynamically reconfigurable embedded systems. Our co-synthesis system, CRUSADE, takes as an input embedded system specifications in terms periodic acyclic task graphs with rate constraints and generates dynamically reconfigurable heterogeneous distributed hardware and software architecture meeting real-time constraints while minimizing the system hardware cost. We identify the group of tasks for dynamic reconfiguration of programmable devices and synthesize efficient programming interface for reconfiguring reprogrammable devices. Real-time systems require that the execution time for tasks mapped to reprogrammable devices are managed effectively such that real-time deadlines are not exceeded. To address this, we propose a technique to effectively manage delay in reconfigurable devices. Our approach guarantees that the real-time task deadlines are always met. To the best of our knowledge, this is the first co-synthesis algorithm which targets dynamically reconfigurable embedded systems. We also show how our co-synthesis algorithm can be easily extended to consider fault-detection and fault-tolerance. Application of CRUSADE and its fault tolerance extension, CRUSADE-FT to several real-life large examples (up to 7400 tasks) from mobile communication network base station, video distribution router, a multi-media system, and synchronous optical network (SONET) and asynchronous transfer mode (ATM) based telecom systems shows that up to 56% system cost savings can be realized.

Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors [p. 105]

R. Leupers

This paper presents a new code optimization technique for a class of embedded processors. Modern embedded processor architectures show deep instruction pipelines and highly parallel VLIW-like instruction sets. For such architectures, any change in the control flow of a machine program due to a conditional jump may cause a significant code performance penalty. Therefore, the instruction sets of recent VLIW machines offer support for branch-free execution of conditional statements in the form of so-called conditional instructions. Whether an if-then-else statement is implemented by a conditional jump scheme or by conditional instructions has a strong impact on its worst-case execution time. However, the optimal selection is difficult particularly for nested conditionals. We present a dynamic programming technique for selecting the fastest implementation for nested if-then-else statements based on estimations. The efficacy is demonstrated for a real-life VLIW DSP.

Session 2E: Embedded Core Test Approaches

This session brings a number of solutions for testing embedded cores. From delay fault testing to functional testing of cores used in today's system-on-chip.

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks [p. 112]

D. Nikolos, H. Vergos, T. Haniotakis, Y. Tsiatouhas

In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the Integrated Circuit (IC) can be used for path delay fault testing of the IC. We show that the testing of the IC for path delay faults can be reduced to the testing of each block. Intellectual Property (IP) blocks are treated as black boxes. The number of the circuit paths that must be tested is almost equal to the sum of the paths that must be tested for each block.

An Effective BIST Architecture for Fast Multiplier Cores [p. 117]

A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian

Wallace tree summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex ICs requires the utilization of a BIST architecture that can be easily synthesized along with the multiplier by the module generator.
In this paper, we introduce an effective BIST architecture for fast multipliers that completely complies with this requirement. The algorithmic BIST patterns that this architecture generates a fault coverage higher than 99%. The required Test Pattern Generator consists of a simple fixed-size binary counter, independent of the multiplier size. Accumulator-based compaction is adopted since multipliers and adders coexist in most datapath architectures.

A CAD Framework for Generating Self-Checking Multipliers based On Residue Codes [p. 122]

I. Noufal, M. Nicolaidis

The basic drawbacks related to the design of self-checking circuits include high hardware cost and design effort. Recent developments on self-checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware cost in self-checking data paths for the majority of basic data path blocks such as, adders, ALUs, shifters, register files, etc. However, parity prediction self-checking multipliers involve a hardware overhead significantly higher than for other blocks. Thus, large multipliers will increase significantly the hardware overhead of the whole data path. Residue arithmetic codes allow to reduce this cost. The tools presented in this paper generate automatically self-checking multipliers using such codes. They complete our tools using parity prediction for various other blocks, and enable automatic generation of low cost self-checking data paths.
Keywords: Self-Checking Circuits, Fault Secure Circuits, Multipliers, Residue Arithmetic Codes.

Session 3A: Use of Combinational Verification

Core techniques of combinational verification may be combined or can be applied to sequential verification problems.

An Efficient Filter-based Approach for Combinational Verification [p. 132]

R. Mukherjee, J. Jain, K. Takayama, M. Fujita, J. Abraham, D. Fussell

We have developed a filter-based framework where several fundamentally different techniques can be combined to provide fully automated and efficient heuristic solutions to verification and possibly other NP-complete problems. Such an integrated methodology is far more robust and efficient than any single existing technique on a wide variety of circuits. Our methodology has been applied to verify the ISCAS 85 benchmark circuits and efficient verification results have been presented on a large set of industrial circuits which could not be verified using several published techniques and commercial verification tools available to us.

Using Combinational Verification for Sequential Circuits [p. 138]

R, Ranjan, V. Singhal, F. Somenzi, R. Brayton

Retiming combined with combinational optimization is a powerful sequential synthesis method. However, this methodology has not found wide application because formal sequential verification is not practical and current simulation methodology requires the correspondence of latches disallowing any movement of latches. We present a practical verification technique which permits such sequential synthesis for a class of circuits. In particular, we require certain constraints to be met on the feedback paths of the latches involved in the retiming process. For a general circuit, we can satisfy these constraints by fixing the location of some latches, e.g., by making them observable. We show that equivalence checking after performing repeated retiming and synthesis on this class of circuit reduces to a combinational verification problem. We also demonstrate that our methodology covers a large class of circuits by applying it to a set of benchmarks and industrial designs.

Combinational Equivalence Checking using Satisfiability and Recursive Learning [p. 145]

J. Marques-Silva, T. Glass

The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been proposed for solving this problem. Still, the hardness of the problem and the ever-growing complexity of logic circuits motivates studying and developing alternative solutions. In this paper we study the application of Boolean Satisfiability (SAT) algorithms for solving the Combinational Equivalence Checking (CEC) problem. Although existing SAT algorithms are in general ineffective for solving CEC, in this paper we show how to improve SAT algorithms by extending and applying Recursive Learning techniques to the analysis of instances of SAT. This in turn provides a new alternative and competitive approach for solving CEC. Preliminary experimental results indicate that the proposed improved SAT algorithm can be useful for a large variety of instances of CEC, in particular when compared with pure BDD-based approaches.

Formally Verified Redundancy Removal [p. 150]

S. Hendricx, L. Claesen

In general, logic redundancy tends to degrade design-quality by introducing additional delays in signal propagation, by increasing the gate count or simply by making the resulting hardware untestable. Since they cannot always be avoided, unwanted redundancies have to be first identified and then removed from our designs. In this paper, an alternative methodology to identify and remove redundancy is proposed, which is based on a formal, symbolic verification strategy. The formal framework underlying our approach aids in identifying redundancies and allows us to guarantee the correctness of their removal.

Session 3B: Gate Level Power Estimation and Optimisation

This session addresses logic synthesis for low power issues. The first paper introduces a set of logic transformations that enable power reductions of gate-level netlists. The second paper proposes a new approach for post layout glitch power minimisation. A novel state encoding algorithm is presented in the third contribution. Finally, the fourth paper deals with peak power estimation methods.

Logic Transformation for Low Power Synthesis [p. 158]

K. Kim, S. Kang, T. Hwang and C. Liu

In this paper, we present a new approach to the problem of local logic transformation for reduction of power dissipation in logic circuits. Based on the finite-state input transition (FIT) power dissipation model, we introduce a cost function which accounts for the effects of input capacitance, input slew rate, internal parasitic capacitance of logic gates, interconnect capacitance, as well as switching power. Our approach provides an efficient way of estimating the global effect of local logic transformations in logic circuits. In our approach, the FIT model for the transitive fanout cells of a locally transformed subcircuit can be reused to measure the global power dissipation by varying the input probabilities of the transitive fanout cells. Local logic transformation is carried out based on compatible sets of permissible functions (CSPF). Experimental results show that local logic transformation based on CSPF using our cost function can reduce power consumption by about 36% on average without increase in the worst-case circuit delay.

Glitch Power Minimization by Gate Freezing [p. 163]

L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino, R. Scarsi

This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-Gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. An important feature of the proposed method is that it can be applied in-place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.

Spanning Tree Based State Encoding for Low Power Dissipation [p. 168]

W. Nöth, R. Kolla

In this paper we address the problem of state encoding for synchronous finite state machines. The primary goal is the reduction of switching activity in the state register. At the beginning the state transition graph is transformed into an undirected graph where the edges are labeled with the state transition probabilities. Next a maximum spanning tree of the undirected graph is constructed, and we formulate the state encoding problem as an embedding of the spanning tree into a Boolean hypercube of unknown dimension. At this point a modification of Prim's maximum spanning tree algorithm is presented to limit the dimension of the hypercube for area constraints. Then we propose a polynomial time embedding heuristic, which removes the restriction of previous works, where the number of state bits used for encoding of a k-state FSM was generally limited to dlog 2 ke. Next a more sophisticated embedding algorithm is presented, which takes into account the state transition probabilities not covered by the spanning tree. The resulting encodings of both algorithms often exhibit a lower switching activity and power dissipation in comparison with a known heuristic for low power state encoding.

Peak Power Estimation using Genetic Spot Optimization for Large VLSI Circuits [p. 175]

M. Hsiao

Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

Session 3C: Special Session -- Virtual Socket Interface Alliance

The first presentation will present the technical objectives and background of the work of VSI Alliance. The driving factors and actual achievements will be shown in the context of actual research, development and standardization trends. The second talk is focused on Virtual prototyping of complete mixed hardware (HW)-software (SW) systems that require well-defined multi-level description of the VC interfaces. The third presentation will introduce the VSI Virtual Component Interface, and show how this can map the transactions used in System Level Design onto a range of on-chip bus implementations for different cost/performance tradeoffs.

Virtual Socket Interface Alliance [p. 182]

R. Seepold

VSI Builds Momentum To Solve Design Reuse Imperative

L. Rosenberg

The VSI System-Level Perspective On The MIX and Match of Virtual Components

M. Genoe

Introduction To Virtual Component Interface

G. Matthew

Session 3E: Fault Diagnosis Techniques for Analogue Circuits

This session presents new techniques to diagnose faults in analogue circuits. The first method consists of using an adaptive tester that learns a reference behaviour in a first step. The second method uses information coming from previous samples to resolve ambiguities. The last method consists of using a non-linear regression model using prior circuit simulations.

A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester [p. 184]

E. Cota, L. Carro, M. Lubaszewski

This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behavior in a first step, and comparing this behavior against the output of the circuit under test in a second step. Considering the same basic structure, the diagnosis method consists on injecting probable faults in a mathematical model of the circuit, and later comparing its output with the output of the real faulty circuit. This method has been successfully applied to a case study, a biquad filter. Component soft, large, and hard deviations, and faults in operational amplifiers were considered. The results obtained from practical experiments with this analog circuit are discussed in the paper.

Minimal Length Diagnostic Tests for Analog Circuits using Test History [p. 189]

A. V. Gomes, A. Chatterjee

In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated to sequentially synthesize the test stimulus for the entire duration of test. We use a novel measurement procedure to resolve ambiguities in the present measurement sample by using class association information from the previous samples. This sequential formulation of test generation problem enables fault dropping and greatly reduces simulation and optimization effort. Additionally, this method is immune to noise and tests can be easily calibrated for use in hardware testers.

Parametric Fault Diagnosis for Analog Systems using Functional Mapping [p. 195]

S. Cherubal, A. Chatterjee

We propose a new Simulation-After-Test (SAT) methodology for accurate diagnosis of circuit parameters in large analog circuits. Our methodology is based on constructing a non-linear regression model using prior circuit simulation, which relates a set of measurements to the circuit's internal parameters. First, we give algorithms to select measurements that give all the diagnostic information about the Circuit-Under-Test (CUT). From these selected measurements, we solve for the internal parameters of the circuit using iterative numerical techniques. The methodology has been applied to several mixed-signal test benchmark circuits and has applications in process debugging for mixed-signal integrated circuits (ICs) as well trouble-shooting and repair of board level systems.

Session 4A: Resource Sharing in Architectural Synthesis

This session addresses different resource sharing approaches. Whereas the first paper concentrates on temporal partitioning of reconfigurable processors, the second paper discusses resource sharing among multiple processes, while the third one deals with optimising the allocation of complex components. The last paper investigates post synthesis formal verification of RTL designs generated by high level synthesis.

Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs [p. 202]

M. Kaul, R. Vemuri

We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. Design space exploration involves selecting a design point for each task from a set of design points for that task to achieve latency minimization of partitioned solutions. We present an iterative search procedure that uses a core ILP (Integer Linear Programming) technique, to obtain constraint satisfying solutions. The search procedure explores different regions of the design space while accomplishing combined partitioning and design space exploration. A case study of the DCT (Discrete Cosine Transform) demonstrates the effectiveness of our approach.

Time Constrained Modulo Scheduling with Global Resource Sharing [p. 210]

C. Jäschke, F. Beckmann, R. Laur

Commonly used scheduling algorithms in high-level synthesis only accept one process at a time and are not capable of sharing resources across process boundaries. This results in the usage of at least one resource per operation type and process. A new method is proposed in order to overcome these restrictions and to share high-cost or limited resources within a process group. This allows the use of less than one resource per operation type and process, while keeping the mutual independence of the involved processes. The method represents an extension of general scheduling algorithms and is not tied to a specific algorithm. It is applied to the time constrained Force-Directed Scheduling algorithm. For this the scope of the scheduling is extended to the processes of the whole system and a two-part modification is applied to the original procedure. A multi-process example illustrates the resource sharing capabilities of the extension.

Polynomial Methods for Allocating Complex Components [p. 217]

J. Smith, G. De Micheli

Methods for performing component matching by expressing an arithmetic specification and a bit-level description of an implementation as word-level polynomials have been demonstrated for combinational circuits. This representation allows the functionality of a specification and existing implementation to be compared. We present extensions to this basic method that allow polynomial models to be constructed for circuits that employ sequential elements as well as feedback. Furthermore, we derive a means of approximating the functionality of non polynomial functions and determining a bound on the error of this approximation. These methods are used to synthesize an Infinite Impulse Response filter from a library of potential implementations.

Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs [p. 223]

N. Mansouri, R. Vemuri

This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/ optimization schemes commonly found in high-level synthesis tools. Performing register optimization as part of synthesis process implies that the mapping between the specification variables and RTL registers is not bijective. We propose a formalization of dynamic variable-register mapping, and techniques based on symbolic analysis and higher-order logic theorem proving for verifying synthesized RTL designs. The proposed verification methodology has been successfully implemented using the PVS theorem prover.

Session 4B: Mixed Signal Characterisation and Test

Problems relating to characterisation and test of complex mixed signal systems will be addressed in this session. The first paper will present a digital partial BIST solution for an AGC that aims to reduce test time and complexity. The second paper will look at characterisation and modelling issues in a new magnetic field sensor and the final two short papers will address the problems of analogue simulation and test response handling.

A Digital Partial Built-In-Self-Test Structure for a High Performance Automatic Gain Control Circuit [p. 232]

A. Lechner, J. Ferguson, A. Richardson, B Hermes

It is now widely recognised that Design-for-Testability and Built-in Self-Test techniques will be mandatory to meet test and quality specifications in next generation mixed signal integrated systems. This paper describes a new digital on-chip post processing function capable of reducing production test time for a high performance automatic gain control circuit by 70%.

Design, Characterization and Modeling of a CMOS Magnetic Field Sensor [p. 239]

L. Latorre, Y. Bertrand, P. Nouet, F. Pressecq, P. Hazard

This paper presents both the design and the characterization of a full CMOS magnetic field sensor. As an alternative to Hall effect sensors, it acts as a microscopic cantilever, deformed under the action of the Lorentz's force.

Fast, Robust DC and Transient Fault Simulation for Nonlinear Analogue Circuits [p. 244]

Z. Yang, M. Zwolinski

The evaluation of analogue and mixed-signal test strategies and design for test techniques requires the fault simulation of analogue circuits. The need to reduce fault simulation time for has resulted in the research into concurrent analogue fault simulation, analogous to digital fault simulation. Concurrent simulation can reduce the simulation time by avoiding repeated construction of the circuit matrix. Fault collapsing and dropping is also desirable. A robust, fast algorithm for concurrent analogue fault simulation is presented in this paper. Three techniques for the automatic dropping of faults have been addressed: a robust closeness measurement technique; a late start rule and an early stop rule. The algorithm has been successfully applied to both DC and transient analyses. A significant increase in the speed of analogue fault simulation has been obtained.

On Analog Signature Analysis [p. 249]

F. Novak, B. Hvala, and S. Klavzar

We formalize the problem of analog data compression and analyze the existence of a polynomial data compression function. Under relaxed conditions we explore the existence of a solution employing digital signature analysis in the analog domain.

Session 4C: System Design Methodologies: Modelling, Analysis, Refinement and Synthesis

The first paper presents main concepts in the electronic system design such as: modelling, analysis and synthesis. The second paper addresses a system synthesis algorithm which partitions and schedules embedded systems specifications to intellectual property cores in an integrated circuit. Finally, the third paper proposes a refinement methodology to move the DSP functions from a floating point to a fixed point representation in the case of implementing these functions in hardware (ASIC).

The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems [p. 256]

A. Jantsch, A. Hemani, S. Kumar

We propose a conceptual framework, called the Rugby Model, in which designs, design processes and design tools can be studied. It is an extension of the Y chart and adds two dimensions for design representation, namely Data and Time. The behavioural domain of Y chart is replaced by a more restricted domain called Computation. The structural and physical domains of Y chart are merged into a more general domain called Communication. A fifth dimension deals with design manipulations and transformations at three abstraction levels. The model shall establish a common understanding of modelling and design process concepts for communication and education in the community. In a case study we illustrate how a design can be characterized with the concepts of the Rugby model.

MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis [p. 263]

R. Dick, N. Jha

In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrated circuit. Given a system specification consisting of multiple periodic task graphs as well as a database of core and integrated circuit characteristics, MOCSYN synthesizes real-time heterogeneous single-chip hardware-software architectures using an adaptive multiobjective genetic algorithm that is designed to escape local minima. The use of multiobjective optimization allows a single system synthesis run to produce multiple designs which trade off different architectural features. Integrated circuit price, power consumption, and area are optimized under hard real-time constraints. MOCSYN differs from previous work by considering problems unique to single-chip systems. It solves the problem of providing clock signals to cores composing a system-on-a-chip. It produces a bus structure which balances ease of layout with the reduction of bus contention. In addition, it carries out floorplan block placement within its inner loop allowing accurate estimation of global communication delays and power consumption.

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement [p. 271]

R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, I. Bolsens

Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies for fixing MSB and LSB weights of fixed point signals. It enables short design cycles by combining the strengths of both analytical and simulation based methods.

Session 4E: High Level Test Synthesis

This session deals with high-level synthesis of testable designs. The first paper presents a technique to test datapath-controller pairs in an integrated fashion. The second paper addresses the issues of module reachability for test purpose during high-level synthesis. The last paper describes a BIST insertion technique used in a partial intrusion BIST environment.

Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs [p. 278]

J. Carletta, M. Nourani, C. Papachristou

This work facilitates the testing of datapath-controller pairs in an integrated fashion, with datapath and controller tested together in a single test session. Such an approach requires less test overhead than an approach that isolates datapath and controller from each other during test. The ability to do an integrated test is especially important when testing core-based embedded systems. The key to the approach is a careful examination of the relationship between techniques for controller synthesis and the types of gate level controller faults that can occur. A method for controller synthesis is outlined that results in a fully testable controller, so that full fault coverage of the controller can be achieved without any need for isolation during test.

Channel-Based Behavioral Test Synthesis for Improved Module Reachability [p. 283]

Y. Makris, A. Orailoglu

We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. Based on the notion of transparency channels, test justification and propagation bottlenecks are revealed for each module in the design. Subsequently, the proposed behavioral test synthesis scheme eliminates, during scheduling, allocation and binding, as many reachability bottlenecks, as possible. Furthermore, it identifies the control states and provides the templates required for translating each module's test into global design test. We demonstrate our scheme on a representative example, unveiling the potential of path analysis based techniques to accurately identify and eliminate module reachability bottlenecks, thus guiding behavioral test synthesis.

Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths [p. 289]

N. Nicolici, B. Al-Hashimi

In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is based on concurrent testing of modules with identical physical information by sharing the test pattern generators in a partial intrusion BIST environment. Furthermore, to reduce the number of signature analysis registers and test application time the same type modules are grouped in test compatibility classes and n-input k-bit comparators are used to check the results. The test application time is computed using an incremental test scheduling approach. An existing test scheduling algorithm is modified to obtain an efficient trade-off between the algorithm complexity and testable design space exploration. A cost function based on both test application time and area overhead is defined and a tabu search-based heuristic capable of exploring the solution space in a very rapid time is presented. To reduce the computational time testable design space exploration is carried out in two phases: test application time reduction phase and BIST area reduction phase. Experimental results are included confirming the efficiency of the proposed methodology.

Session 5A: High-Level System Simulation

The design of a complex system (like that of an MPEG encoder) needs improved simulation, C-based simulation and VHDL-based HW/SW-cosimulation are very promising methods. Three posters present additional approaches for modelling and simulation of complex systems.

A Retargetable, Ultra-Fast Instruction Set Simulator [p. 298]

J. Zhu, D. Gajski

In this paper, we present new techniques which further improve the static compiled instruction set architecture (ISA) simulation by the aggressive utilization of the host machine resources. Such utilization is achieved by defining a low level code generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code generation interface. We are able to perform the simulation at a speed up to 10 ² millions of simulated instructions per second (MIPS). This result is only 1.1--2.5 times slower than the native execution on the host machine, the fastest to the best of our knowledge. Furthermore, the code generation interface is organized to implement a RISC like virtual machine, which makes our tool easily retargetable to many host platforms.

High-Speed Software-based Platform for Embedded Software of a Single-Chip MPEG-2 Video Encoder LSI with HDTV Scalability [p. 303]

K. Ochiai, H. Iwasaki, J. Naganuma, M. Endo, T. Ogura

This paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability. The platform is written in C/C++ languages without any hardware description languages (HDLs) for high-speed simulation. This platform is applicable before writing up complete HDLs. The simulation speed is very fast and more than 600 times faster than compiled HDL simulators using RTL description. Fifty percent of the bugs in the final em-bedded software were located efficiently and quickly, and the design turn-around time was shortened by more than 25%. This platform provides sufficient performance and capability for validating practical embedded software.

Fast Hardware-Software Co-Simulation using VHDL Models [p. 309]

B. Tabbara, M. Sgroi and A. Sangiovanni-Vincentelli, E. Filippi, L. Lavagno

We describe a technique for hardware-software co-simulation that is almost cycle-accurate, and does not require the use of interprocess communication nor a C language interface for the software components. Software is modeled by using behavioral VHDL constructs, annotated with timing information derived from basic block-level timing estimates. Hardware is also modeled in VHDL, and can be either pre-existing Intellectual Property or synthesized to RTL from a functional specification. Execution of the VHDL processes modeling software tasks is coordinated by a process emulating the target RTOS behavior. The effects of changing the hardware/software partition can be quickly estimated by changing a process parameter defining its target implementation and the processor on which it is running.

Session 5B: Analogue Circuit Sizing and Synthesis

New developments in analogue circuit sizing and synthesis are discussed, both at the level of basic circuits and higher levels. First, a systematic biasing method is presented. Next, an automatic sizing approach that considers structural constraints. Finally, constraint transformation at higher levels is described.

Systematic Biasing of Negative Feedback Amplifiers [p. 318]

C. Verhoeven, A. van Staveren

A biasing method is described, intended to make automated biasing of at least some classes of analog circuits straightforward. It has been tested for linear amplifiers, though it is not restricted to that class. A systematic way to introduce bias sources in a circuit is discussed. Also methods for reducing the number of bias sources and bias feed-back loops are given. Application of the method has shown that at least for the class of amplifiers the theory is well suited for automation.

Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints [p. 323]

R. Schwencker, J. Eckmueller, H. Graeb, K. Antreich

In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and are introduced as structural constraints into the sizing process. Systematic consideration of these structural constraints during the automatic sizing prevents pathologically sized circuits and speeds up the automatic sizing. The sizing is done with a sensitivity-based, iterative trust region method.

Hierarchical Constraint Transformation using Directed Interval Search for Analog System Synthesis [p. 328]

N. Dhanwada, A. Nunez-Aldana, R. Vemuri

In this paper, we present a hierarchical approach for constraint transformation. The important features of this are: a genetic algorithm (GA) based search engine that computes design parameter ranges, a hierarchically organized characterization mechanism based on the concept of directed intervals that assists the search engine and an analog performance estimator. Experiments were conducted comparing the hierarchical approach with a flat bottom-up one. The results obtained demonstrate the effectiveness of the former approach. Experimental results highlighting the impact of using the characterization information within the constraint transformation process are also presented.

Session 5C: VHDL-AMS and HDL Interoperability

The papers in this session cover various aspects of analogue and mixed-signal modelling using VHDL and VHDL-AMS as well as mixed-language hardware description issues, VHDL-Verilog interoperability and formal semantics.

A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems [p. 338]

A. Doboli, R. Vemuri

This paper presents a complete method for automatically translating VHDL-AMS behavioral-specifications of analog systems into op amp level net-lists of library components. We discuss the three fundamental aspects, that pertain to any behavioral synthesis environment: the specification language, the rules for compiling language constructs into a technology-independent, intermediate representation, and the synthesis (mapping) of representations to net-lists (topologies) of library components, so that performance constraints are satisfied. We motivate the effectiveness of the method by presenting our synthesis results for 5 examples.

Reasoning about VHDL and VHDL-AMS using Denotational Semantics [p. 346]

P. Breuer, N. Madrid, C. Kloos, J. Bowen, R. France, M. Petrie

This paper introduces a denotational semantics for a core of the draft IEEE standard analog and mixed signal design language VHDL-AMS, and derives general results about the behaviour of VHDL-AMS programs from it. We include, for example, a demonstration that VHDL-AMS parallelism is benign in the absence of shared initializations. As proof of concept we have built an interpreted simulator that prototypes the semantics and which runs multiprocess mixed analog and digital descriptions correctly.
Keywords: Language design, VHDL-AMS, Language semantics, mixed-signal simulation.

A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstract State Machine [p. 353]

H. Sasaki

A formal semantic analysis for Verilog-HDL and VHDL is provided in order to give the simulation model especially focusing on signal scheduling and timing control mechanism. Our semantics is faithful to LRM and is expected to become a coherent first step for a future semantic interoperability analysis on multi-semantic-domain such as Verilog-AMS and VHDL-AMS. By ignoring the differences of the two simulation cycles, we can use the common semantic functions and the common simulation cycle.

Session 5E: Transistor Level Test

Transistor level DFT for Current Mode Logic is addressed in the first paper. The next paper deals with pass-transistor implementations of self-checking circuits. The last paper presents a new approach for parametric on-chip testing.

Design for Testability Method for CML Digital Circuits [p. 360]

B. Antaki, Y. Savaria, N. Xiong, S. Adham

This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitors all gate output swings and flags all abnormal voltage excursions. These detectors cover classes of faults that cannot be tested by stuck-at testing methods only. Circuit simulations have shown that abnormal gate output excursions caused by the presence of a defect are common with CML. We also show that this technique works well below "at-speed" frequencies. Finally, variants of the built-in detectors with reduced area overhead are proposed.

On the Design of Self-Checking Functional Units based on Shannon Circuits [p. 368]

M. Favalli, C. Metra

This paper investigates the application of Shannon (BDD) circuits, that feature interesting low-power capabilities, to the design of self-checking functional units. A technique is proposed that, by using a time redundancy approach, makes this kind of circuits totally self-checking with respect to stuck-at faults. For a set of possibly used pass-transistor-based CMOS implementations, we show that the totally self-checking or the strongly fault secure properties hold for a wider set of realistic faults, including transistors stuck-open/on and bridgings.

Parametric Built-In Self-Test of VLSI Systems [p. 376]

D. Niggemeyer, M. Rüffer

Conventionally, Automatic Test Equipment (ATE) has been used for parametric tests of VLSI systems to determine the influence of clock speed, supply voltage, and temperature on the specified functionality of the circuit under test. This method is likely to become infeasible in the near future due to an aggressive drive to increased Overall Timing Accuracy (OTA), as predicted in the SIA Roadmap. In this paper, a method for Parametric Built-In Self-Test using on-chip Phase-Locked Loops (PLLs) is presented which is capable of overcoming the timing accuracy problem. A PLL-based test circuitry to determine the maximum frequency is described. Design constraints of the PLL control system, such as stability and resolution, are discussed for a specific design using 0.35µm CMOS technology. The functionality of the self-test circuitry is demonstrated to be competitive with parametric ATE tests such as Global Search Track without the need for expensive test equipment.

Session 6A: Hot Topic -- Hardware Synthesis From C/C++ Models

Designers often use programming languages to model hardware, because of the ease of simulating the high-level behaviour (possibly in conjunction with software), of migrating software code to hardware and of using legacy models. Hardware synthesis from programming language models is challenging, due to the lack of an underlying hardware semantics. Nevertheless, synthesis from C/C++ subsets has become reality, and this session wil present current approaches, their advantages and limitations.

Hardware Synthesis from C/C++ Models [p. 382]

G. De Micheli

Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of flexibility and fast simulation of models described with programming languages. At the same time, the mismatch (of software languages) in expressing power (for hardware systems) has caused several difficulties. In the recent past, novel approaches have helped in reducing the semantic gap, and in easing the creation of design flows that support system-level specifications in C/C++.

C for System Level Design [p. 384]

G. Arnout

Few people disagree with the fact that today about 80% of a system is software running on a "platform" of general purpose or custom processors (CPU and/or DSP) tightly coupled with unique dedicated hardware. This makes C (or C++) an obvious candidate for a system level design language. Without good hardware/software partitioning tools and support for C-based hardware design, the software content may have to increase by necessity. With the right hardware support a system team has the flexibility to make cost, performance, power trade-offs and decide later in the game how much of the system is software and how much is hardware. Another issue is legacy software and hardware. Legacy C software is well understood but legacy hardware is usually only available as RTL (Verilog or VHDL) at best. Therefore the ideal system level design language is C (or C++) based, accommodates hardware design but also co-exists with the vast legacy of Verilog and VHDL based re-usable hardware. CoWare N2C is practical solution, used in real life design around the world, that a) preserves the C software development paradigm for software people, b) adds the necessary clocking to C to enable hardware designers to move C functionality into a hardware architecture, and c) co-exists (for co-design and co-simulation) with existing hardware in Verilog or VHDL.

Hardware Synthesis from C/C++ [p. 387]

A. Ghosh, J. Kunkel, S. Liao

Before attempting to synthesize hardware from a programming language like C or C++, we need to introduce additional semantics to be able to describe hardware behavior accurately. In particular, concurrency, reactivity, communication mechanisms, and event handling semantics need to be added. Also, a synthesizable subset of the language needs to be defined, together with synthesis semantics for programming language constructs. With these enhancements, it is possible to create C/C++ descriptions of hardware at the well-understood RTL and behavioral levels of abstraction, providing an opportunity to leverage existing, mature hardware-synthesis technology that has been developed in the context of HDL based synthesis to create a C/C++ synthesis system. In this paper, we will present some of the key ingredients of a C/C++ synthesis system and elaborate on the challenges of hardware synthesis from C/C++.

C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber" [p. 390]

K. Wakabayashi

This paper presents C-based behavioral hardware design environment. Initially, we discuss motivations of the design environment and the merits and demerits of the C language as a behavioral hardware language. The configuration of the environment of which main component is a behavioral synthesizer "Cyber", is presented. Then, we explain various aspects of the C-based design method using some design experiences for both control dominated circuits and data intensive circuits. Lastly, we summarize current status of our C-based design and discuss problems to diffuse C-based design method widely.

Session 6B: Analogue Modelling and Simulation

The first paper deals with substrate coupling modelling. The second paper presents a new model for high-level performance estimation of converters. The following two papers present qualitative performance modelling for simulation oriented synthesis and efficient symbolic performance modelling.

Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's [p. 396]

J. Costa, L. Silveira, M. Chou

Accurate modeling of noise coupling effects due to crosstalk via the substrate is an increasingly important concern for the design and verification of mixed analog-digital systems. In this paper we present a technique to accelerate the model computation using BEM methods that can be used for accurate and efficient extraction of substrate coupling parameters in mixed-signal designs.

A Power Estimation Model for High-Speed CMOS A/D Converters [p. 401]

E. Lauwers, G. Gielen

Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits information from reported designs is presented. The estimator is an analytical expression which is independent of the actual topology used and can easily be updated with new published designs. Experimental results show a good predictor accuracy of better than a factor 2.2 for most designs.

An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis [p. 406]

A. Nunez-Aldana, R. Vemuri

Critical to the automation of analog circuit systems is the estimation process of performance parameters which are used to guide the topology selection and circuit sizing processes. This paper presents a methodology to improve the effectiveness of the CMOS analog system circuit synthesis search process by developing an Analog Performance Estimator (APE) tool. APE is capable of accepting the design parameters of an analog circuit and determine its performance parameters along with anticipated sizes of all the circuit elements. The APE is structured as a hierarchical estimation engine containing performance models of analog circuits at various levels of abstraction.

An Accurate Error Control Mechanism for Simplification before Generation Algorithms [p. 412]

O. Guerra, J. Rodríguez-García, E. Roca, F. Fernández, A. Rodríguez-Vázquez

The use of simplification before generation techniques to enable the approximate symbolic analysis of large analog circuits is discussed. This paper introduces an error control mechanism to drive the circuit reduction, which overcomes the accuracy problems of previous approaches. The features and efficiency of the new methodology are demonstrated through several practical examples.

Session 6C: Hot Topic -- Chip Package Co-Design

Traditionally there has been very limited interaction between IC design and packaging design. It is expected however, that for some applications the increasingly aggresive system performance requirements will necessitate a concurrent design of ICs and packages in the future. For high-performant systems, chip-package co-design means the optimal distribution of the routing between on-chip and off-chip interconnections. Also, future telecom products will benefit from the availiability of these integrated passives to achieve lower cost, better performance and faster development time. Finally, the modeling and simulation problems have to be addressed. An overview of existing solution techniques, such as efficient extraction algorithms and reduced-order modeling methods will be presented. Current challenges and open problems will also be discussed.

Efficient Techniques for Modeling Chip-level Interconnect, Substrate and Package Parasitics [p. 418]

P. Feldman, S. Kapur, D. Long

Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computationally expensive. In this paper, we discuss some recent novel schemes for extraction and reduced order modeling that help overcome this computational bottleneck.

Potentials of Chip-Package Co-Design for High-Speed Digital Applications [p. 423]

G. Tröster

The inherent potentials of the Si technology are limited by the low interaction with packaging. Co-design as the symbiosis between the ICs and appropriate high-density packaging offers lower RC line delay, improved SSN and lower costs compared to single-chip approaches. The distribution of the system functionality between IC and the packaging level opens up new vistas in future electronic design and system architecture.

A Single-Package Solution for Wireless Transceivers [p. 425]

P. Wambacq, S. Donnay, H. Ziad, M. Engels, H. De Man, I. Bolsens

Although a single-chip solution seems to be ultimate goal for the design of wireless transceivers, there are many reasons to believe that this approach is not feasible for high-performance applications. Especially the RF front-ends of these transceivers require components that are difficult to combine into one single chip. As an alternative we propose a single-package solution that contains different components that are interconnected with a multi-chip module (MCM) interconnect technology. By implementing passive front-end components directly into this interconnect technology, in-stead of using external commercial components, a cost-effective realization of the front-end can be obtained with a higher performance or a lower power consumption.

Session 6E: Panel -- Scaling Towards Nanometer Technologies: Design for Test Challenges

The continuous scaling in microelectronics results in numerous challenges that test technology should overcome, such as reduced noise margins; reduced accessibility; increased inadequacy between IC generations and Automatic Test Equipment, and complex defect behavior, making performance and other spurious faults predominant. The panel will discuss the relevance of these challenges to nanometer technologies and try to identify potential solutions for them.

Scaling Deeper to Submicron: On-Line Testing to the Rescue [p. 432]

M. Nicolaidis, Y. Zorian

Session 7A: Functional Verification

Functional correctness assessment represents one of the primary and most time-consuming tasks of the complete design process. In this session, two different approaches to the problem are presented. The first one describes a rigorous methodology for microprocessor design verification. The second presents a new approach for functional vector generation based on a precise behavioural error model and a controllability metric on VHDL code coverage evaluation.

Functional Verification Methodology for Microprocessors using the Genesys Test-Program Generator -- Application to the X86 Microprocessors Family [p. 434]

L. Fournier, Y. Arbetman, M. Levinger

Even though the importance of microprocessor design verification is widely acknowledged, no rigorous methodology is being commonly followed for its realization. This paper attempts to delineate such a methodology, and shows how it is promoted by Genesys, an automatic pseudo-random test-program generator. The methodology relies on a verification plan which induces smart sets of tests that carry out the verification tasks. The paper reports on an application of this methodology, using Genesys, to verify an x86 design and describes, in particular, how this methodology could have helped to avoid known escape bugs, such as the recent two infamous Pentium Floating Point bugs.

Symbolic Functional Vector Generation for VHDL Specifications [p. 442]

F. Ferrandi, F. Fummi, L. Gerli, D. Sciuto

Verification of the functional correctness of VHDL specifications is one of the primary and most time consuming task of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the specification by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral fault model. First, we generate a reduced number of functional test vectors for each process of the specification which allow complete code statement coverage and bit coverage, allowing the identification of possible redundancies in the VHDL process. Then, through the definition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when it is interconnected to other processes. If this is not the case, the analysis of the non-applicable inputs provides identification of possible code redundancies and design errors. Experimental results show that bit coverage provides complete statement coverage and a more detailed identification of possible design errors.

Session 7B: Bit-Level Logic and Analogue Simulation

Decision Diagrams -- related to the well-known BDDs -- offer a new method for improved simulation efficiency both in the analogue and digital area. The symbolic calculation of the transfer function of linear systems gives additional insight into the main functionality of analogue circuits. Precise delay models (covering hazards and glitches) and effective bitparallel evaluation is the basis of switching activity simulation especially as applied in low-power design.

Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams [p. 448]

X. Tan, C. Shi

A new approach is proposed to generate interpretable symbolic expressions of small-signal characteristics for large analog circuits. The approach is based on a complete, exact, yet compact representation of symbolic expressions via determinant decision diagrams (DDDs). We show that two key tasks of generating interpretable symbolic expressions -- term de-cancellation and term simplification -- can be performed in linear time in terms of the number of DDD vertices. With the number of DDD vertices many-orders-of-magnitude less than the number of product terms, the proposed approach has been shown to be much more efficient than other start-of-the-art approaches.

Cycle-based Simulation with Decision Diagrams [p. 454]

R. Ubar, J. Raik, A. Morawiec

This paper addresses the problem of efficient functional simulation of synchronous digital systems. A technique based on the use of Decision Diagrams (DD) for representing the functions of a design at RT and behavioural level is introduced. The DD evaluation technique is combined with cycle based simulation mechanism to achieve the significant speed up of the simulation execution. Experimental results are provided for demonstrating the efficiency gain of this method in comparison to the event-driven simulation.

Efficient Switching Activity Simulation under a Real Delay Model using a Bitparallel Approach [p. 459]

M. Bühler, M. Papesch, K. Kapp and U. Baitinger

Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will be presented. The combination of event driven and bitparallel simulation allows for high accuracy due to the real delay model of the former while maintaining the speedup of the latter. This is demonstrated by detailed experimental results.

Session 7E: Partial and Boundary Scan Test

An original 3-phase procedure based on structural and functional analysis for partial scan is presented, together with a novel solution to execute dynamic interconnect test at the board level.

Full Scan Fault Coverage with Partial Scan [p. 468]

X. Lin, I. Pomeranz, S. Reddy

In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the ip- ops. New measures are used to guide the ip- op selection during the procedure. The proposed procedure is applied to the ISCAS-89 and the ADDENDUM-93 benchmark circuits. For all the circuits, it is possible to achieve the same fault coverage as that for full scan while scanning a portion of the ip- ops.

At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks [p. 473]

J. Shin, H. Kim, S. Kang

As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on board-level interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.

Session 8A: New Languages for System Specification and Design

This session presents new languages for heterogeneous system specifications, to support design space exploration and an optimisation strategy for synthesis of data types from high level specifications.

OpenJ: An Extensible System Level Design Language [p. 480]

J. Zhu, D. Gajski

There is an increasing research interest in system level design languages which can carry designers from specification to implementation of system-on-a-chip. Unfortunately, two of the most important goals in designing such a language, are at odds with each other: Heterogeneity requires components of the system to be captured precisely by domain specific models to simplify analysis and synthesis; simplicity requires a consistent notation to avoid confusion. In this paper, we focus on our effort in resolving this dilemma in an extensible language called OpenJ. In contrast to the conventional monolithic languages, OpenJ has a layered structure consisting of the kernel layer, which is essentially an object oriented language designed to be simple, modular and polymorphic; and the open layer, which exports parameterizable language constructs; and the domain layer which precisely captures the computational models essential for embedded systems. The domain layer can be provided by vendors via a common protocol defined by open layer which enables the supersetting or/and subsetting of the kernel. A compiler has been built for this language and experiments are conducted for popular models such as synchronous, discrete event and dataflow.

EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability [p. 485]

A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, A. Nicolau

We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-on-Chip (SOC) and automatic generation of a retargetable compiler/ simulator toolkit. Key features of our language-driven design methodology include: a mixed behavioral/structural representation supporting a natural specification of the architecture; explicit specification of the memory subsystem allowing novel memory organizations and hierarchies; clean syntax and ease of modification supporting architectural exploration; a single specification supporting consistency and completeness checking of the architecture; and efficient specification of architectural resource constraints allowing extraction of detailed reservation tables for compiler scheduling. We illustrate key features of EXPRESSION through simple examples and demonstrate its efficacy in supporting exploration and automatic software toolkit generation for an embedded SOC codesign flow.

Data Type Analysis for Hardware Synthesis from Object-Oriented Models [p. 491]

M. Radetzki, A. Stammermann, W. Putzke-Röming, W. Nebel

Object-oriented modeling of hardware promises to help deal with design complexity through higher abstraction and better support for reuse. Whereas simulation of such models is rather easy to achieve, synthesis turns out to require the application of quite sophisticated techniques. In this paper, we devise a solution of the foremost problem, optimized synthesis of object-oriented data types. The outlined algorithms have been implemented for an obect-oriented dialect of VHDL and may also contribute, possibly in a co-design context, to synthesis from languages such as C++ or Java. We explain our synthesis methods and show their impact with the example of a microprocessor model.

Session 8B: Circuit Analysis and Design

The first paper presents a knowledge enriched approach for signal integrity analysis. Automatic recognition and modelling of logic gates out of a switch-level network is the topic of the second paper. Finally, the design of fast arithmetic circuits using GaAs based Feed through Logic is presented.

How to use Knowledge in an Analysis Process [p. 498]

H. Holzheuer

An efficient design and analysis process is based on an enormous amount of knowledge and information. Therefore, tools and techniques for knowledge acquisition, representation, and visualisation have to be integrated into the overall design process but they don't have to be treated as separate components. The variety of knowledge sources and its dependency on the environment lead to a complex integration task. This paper presents a knowledge enriched approach to support a signal integrity analysis process.

Digital MOS Circuit Partitioning with Symbolic Modeling [p. 503]

L. Ribas, J. Carrabina

This paper presents a method to automatically recognize and model single and multi-output logic gates out of a switch-level network, even for irregular transistor structures. Result subcircuit models are directly used in a symbolic simulator for circuit analysis purposes. Other applications of derived netlists cover switch-level simulation acceleration and test generation tool enhancement.

High Speed GaAs Subsystem Design using Feed through Logic [p. 509]

J. Montiel-Nelson, V. de Armas, R. Sarmiento, A. Núñez, S. Nooshabadi

In this paper design of fast arithmetic circuits using GaAs based Feed Through Logic (FTL) family [1] is presented. A modified version of FTL termed Differential FTL (DFTL) is introduced and basic aspects of design methodologies using FTL are discussed. A 4-bit ripple-carry adder is designed and its performance is evaluated against other similar reported works in terms of, device count, chip area, delay, clock rate, and power consumption. It is shown how arithmetic circuits based on FTL outperform the evaluated performance. A 4-bit magnitude comparator is de-signed and performance evaluated against four cascaded 1-bit comparators.

Session 8C: Logic Synthesis

This session contains four papers which advance the state-of-the-art in various basic logic synthesis techniques.

Integrating Symbolic Techniques in ATPG-based Sequential Logic Optimization [p. 516]

E. San Millán, L. Entrena, J. Espejo, S. Chiusano, F. Corno

This paper presents a new integrated approach to logic optimization for sequential circuits. The approach is based on the Redundancy Addition and Removal algorithm, which is based on Automatic Test Pattern Generation (ATPG) techniques, and improves it using Symbolic Techniques based on BDDs. The advantage of the integrated approach lies in the ability of Symbolic Techniques to provide exact and extensive information about the sequential behavior of the portion of the circuit that is of interest to the logic optimization algorithm. Experimental results are provided that show the superiority of the approach to the original ATPG-based optimization approach.

An Algorithm for Face-Constrained Encoding of Symbols using Minimum Code Length [p. 521]

M. Martínez, M. Avedillo, J. Quintana, J. Huertas

Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column based algorithm to solve this optimization problem. The new algorithm targets economical implementation of face constraints unlike conventional algorithms which do not care about infeasible ones. Experimental results that demonstrate the superiority of the new method versus conventional tools and a previous algorithm specifically developed for the minimum length encoding problem are shown. An state assignment tool which core is the new algorithm is evaluated by implementing an standard benchmark of sequential circuits. It compares very favorably to well known tools like NOVA.

Algorithms for Solving Boolean Satisfiability in Combinational Circuits [p. 526]

L. Guerra e Silva, L. Silveira, J. Marques-Silva

Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover, Boolean Satisfiability is in the core of algorithms for solving Binate Covering Problems. This paper describes how Boolean Satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean Satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.

Wavefront Technology Mapping [p. 531]

L. Stok, M. Iyer, A. Sullivan

The wavefront technology mapping algorithm leads to a very simple and efficient implementation that elegantly de-couples pattern matching and covering but circumvents that patterns have to be stored for the entire network simultaneously. This coupled with dynamic decomposition enables trade-off of many more alternatives than in conventional mapping algorithms. The wavefront algorithm maps optimally for minimal de-lay on DAGs when a gain based delay model is used. It is optimal with respect to the arrival times on each path in the network. A special timing mode for multi-source nets allows minimization of other (non-delay) metrics as a secondary objective while maintaining delay optimality.

Session 8E: IDDX Testing and Defect Modelling

Defect modelling and defect detection are very important for test. This session explores traditional IDDQ testing plus IDDT testing, where T = transient. In addition, defect-oriented fault simulation is presented.

On-Chip Transient Current Monitor for Testing of Low-Voltage CMOS IC [p. 538]

V. Stopjaková, H. Manhaeve, M. Sidiropulos

In this paper, on-chip test circuitry performing the transient supply current measurement is presented. The introduced principle makes uses of the parasitic resistance of the supply connection to sense the dynamic supply current. Thus, the monitor does not cause any additional power supply voltage degradation and provides detection capabilities for open defects that usually cause a significant reduction of the I''7 current. The proposed monitor does not affect the performance of the CUT and can be efficiently used to test low-voltage CMOS circuits. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design has been implemented together with an experimental CMOS circuit using Alcatel-Mietec 0.7 mm CMOS technology and its processing is in progress. Evaluation results of the prototype test chips will be presented at the conference.

Exploring the Combination of I_DDQ and i_DDt Testing: Energy Testing [p. 543]

J. Rius and J. Figueras

The feasibility of combining I_DDQ and i_DDt testing to detect defective circuits by measuring the energy consumed by the tested circuit is considered. The energy chronogram of a circuit is used as an Energy Signature which makes it possible to distinguish between defect-free and defective circuits. Exploratory implementation of the proposed method is presented and experimental results obtained from in-house full custom circuits and commercially available circuits are discussed.

Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip using HDL [p. 549]

M. Santos, J. Teixeira

The validation of high-quality tests requires Defect-Oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel tool, veriDOFS, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults. Design hierarchy is exploited, by pre-computing a test view of each cell in a library. The good trade-off accuracy / tractability, as well as the computational efficiency of the new tool are demonstrated by means of structural benchmarks up to 100,000 transistors and 300,000 realistic faults.

Session 9A: HW/SW Interface Synthesis and Partitioning

The papers presented in this session concentrate on interface synthesis and partitioning of HW/SW embedded systems. The first paper combines software synthesis and automatic HW/SW interface generation to meet hard real-time constraints for digital communication systems. Generation of the software part of the HW/SW interface is the topic of the second paper. The third paper discusses the use of dynamic programming for HW/SW partitioning and mapping of communicating processes.

Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints [p. 556]

S. Vercauteren, D. Verkest, J. Van Der Steen

This paper presents an orchestrated combination of software synthesis and automatic hardware/software interface generation to meet hard real-time constraints. The target applications are digital communication systems, which are specified as concurrent communicating processes. The overall approach is theoretically founded and is demonstrated on an industrial strength design, with promising results.

Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification [p. 562]

M. O'Nils, A. Jantsch

We present a method for generation of the software part of a HW/SW interface (i.e. the device drivers), which separates the behaviour of the interface from the architecture dependent parts. We do this by modelling the behaviour in ProGram (a grammar based protocol specification language) and capture the processor and OS kernel parts in separate libraries. By separating the behaviour from the architectural specific parts, compared to other approaches up to 50% development time can be saved the first time the component is used, and up to 98% for each time the interfaced component is reused.

Codex-dp: Co-Design of Communicating Systems using Dynamic Programming [p. 568]

J. Chang, M. Pedram

In this paper, we present a novel algorithm based on dynamic programming with binning to find, subject to a given deadline, the minimum-cost coarse-grain hardware/ software partitioning and mapping of communicating processes in a generalized task graph. The task graph includes computational processes which communicate with each other by means of blocking/nonblocking communication mechanisms at times including, but also other than, the beginning or end of their lifetime. The proposed algorithm has been implemented. Experimental results are reported and discussed.

Session 9B: Physical Design Issues

In this session three different aspects of physical design are discussed. The first paper presents a set of analytical formulations for 3D modelling of interlayer capacitances. In the second paper the sequence-pair approach is applied to systematically remove overlaps between placed objects. An improved iterative partitioning method for FPGAs is proposed in the third paper.

Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts [p. 576]

A. Toulouse, D. Bernard, C. Landrault, P. Nouet

This paper introduces a set of analytical formulations for 3D modelling of inter-layer capacitances. Efficiency and accuracy are both guaranteed by the process characterization approach. Analytical modelling of interconnect capacitances is then demonstrated to be an helpful alternative to lookup tables or numerical simulations.

Post-Placement Residual-Overlap Removal with Minimal Movement [p. 581]

S. Nag, K. Chaudhary

In this paper we present a novel approach for removing residual overlaps among blocks. We start out by representing the placement in the sequence pair form and describe transformations to the sequence pair to make the placement feasible. This is followed by a distance-based slack allocation to generate a new placement with no overlaps, while being as close to the original placement as possible. Our results demonstrate the efficacy of our approach in transforming layouts with overlaps to overlap-free layouts with minimal object movement.

Iterative Improvement based Multi-Way Netlist Partitioning for FPGAs [p. 587]

H. Krupnova, G. Saucier

This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed in [12], but instead of using the replication and re-optimization, it takes force of the classical iterative improvement partitioning techniques ([4], [14]). The basic effort consists in guiding the classical algorithms in their solution space exploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solution and carefully tuning the basic parameters of classical algorithms such as definition of size constraints for feasible moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results comparable to the best published results {[12], [15]), and even outperforms them for biggest benchmarks.

Session 9C: Reliability and Symmetry in Architectural Synthesis

The first paper discusses the synthesis of reliable self recovering architectures while avoiding redundancies in the controller. The last two papers exploit symmetries in architectural synthesis in order to speed -up the design tools.

Self Recovering Controller and Datapath Codesign [p. 596]

S. Hamilton, A. Orailoglu, A. Hertwig

As society has become more reliant on electronics, the need for fault tolerant ICs has increased. This has resulted in significant research into both fault tolerant controller design, and mechanisms for datapath fault tolerance insertion. By treating these two issues separately, previous work has failed to address compatibility issues, as well as efficient codesign methodologies. In this paper, we present a unified approach to detecting control and datapath faults through the datapath, along with a method for fault identification and reconfiguration. By detecting control faults in the datapath, we avoid the area and performance overhead of detecting control faults through duplication or error checking codes. The result is a complete design methodology for self recovering architectures capable of far more efficient solutions than previous approaches.

Identification and Exploitation of Symmetries in DSP Algorithms [p. 602]

C. van Eijk, E. Jacobs, B. Mesman, and A. Timmer

In many algorithms, particularly those in the DSP domain, certain forms of symmetry can be observed. To efficiently implement such algorithms, it is often possible to exploit these symmetries. However, current hardware and software compilers show deficiencies, because they cannot identify them. In this paper we, we propose two techniques to automatically detect and utilize symmetry. Both techniques introduce sequence edges between operations such that the feasibility of the scheduling problem is preserved, while the symmetry is broken. In combination with existing techniques for constraint analysis, this enhances the quality of compilers considerably, as is shown by benchmark results.

Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation [p. 609]

L. dos Santos, J. Jess

Emerging design problems are prompting the use of code motion and speculation in high-level synthesis to shorten schedules and meet tight time-constraints. Unfortunately, they may increase the number of states to an extent not always affordable for embedded systems. We propose a new technique that not only leads to less states, but also speeds up scheduling. Equivalent states are predicted and merged while building the finite state machine. Experiments indicate that flexible code motions can be used, since our technique restrains state expansion.

Session 9D: Panel -- Single Chip or Hybrid System Integration ?

Single Chip or Hybrid System Integration ? [p. 616]

I. Bolsens

Panelists: Wojtek Maly, CMU, USA; Ludo Deferm, IMEC, B; Jo Borel, ST, F; Harry Veendrick, Philips, NL

If we continue to increase the complexity of ICs at the same pace as we did from 1960 onwards, this complexity will have reached half a billion transistors per chip, within a decade from now. And the clock period is `expected' to be well below the one nanosecond. This panel will discuss future trends of cost, power, speed, reliability and signal integrity. If we don't believe these excessive numbers, design styles and methods as well as integration technology need to be changed to cope with the complexity and performance of future embedded systems This panel will discuss the consequences for deep-submicron IC design and possible way outs for the roadblocks.

Session 9E: Testing Regular Structures and Delay Faults

This session includes presentations on minimum length test patterns for SRAM-based FPGA structures, industrial evaluation of a large number of memory test algorithms on DRAM circuits, and functional ATPG tools for delay faults.

Testing the Configurable Interconnect/Logic Interface of SRAM-based FPGA's [p. 618]

M. Renovell, J. Portal, J. Figueras, Y. Zorian

The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. In usual SRAM-based FPGAs, Configurable Interface Modules (CIMs) can be found between the global interconnect and inputs of the logic cells (Input CIMs) or between output of the logic cells and the global interconnect (Output CIMs). It is demonstrated that an input CIM that connects N ⁱⁿ segments to a logic cell input requires N ⁱⁿ test configurations and that an output CIM that connects a logic cell output to N ^out segments requires 2 test configurations. Then, it is proven that a set of K ⁱⁿ input CIMs can be tested in parallel making the number of required test configurations equal to N ⁱⁿ. In the same way, a set of K ^out output CIMs is shown to require only 2 test configurations if N ^out > K ^out . Finally, it is shown that the complete mXm array of logic cells with K ⁱⁿ input CIMs and K ^out output CIMs can be tested with only N ⁱⁿ test configurations using the XOR tree and shift register structures.

Industrial Evaluation of DRAM Tests [p. 623]

A. van de Goor, J. de Neef

This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering more different functional faults) also have a higher fault coverage. However, the currently used fault models still leave much to be explained; e.g., the used data backgrounds and address orders show an unexplainable large variation in fault coverage.

ATPG Tools for Delay Faults at the Functional Level [p. 631]

M. Michael, S. Tragoudas

We propose and evaluate two frameworks for functional level ATPG for delay faults in combinational circuits. Although functional delay fault models have been recently proposed [9, 13, 10], no systematic methodologies for ATPG have been presented in the literature. The proposed frameworks apply to any proposed fault model, and utilize established techniques such as Reduced Ordered Binary Decision Diagrams (ROBDDs) and Boolean Satisfiability (SAT).

Session 10A: Retiming

This session presents three papers which extend the usability of retiming in a synthesis environment.

Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence [p. 638]

P. Kalla, M. Ciesielski

This paper presents a retiming and resynthesis technique for cycle-time minimization of sequential circuits circuits with feed-backs (finite state machines). Operating on the delay critical paths of the circuit, we perform a set of controlled local retimings of registers across fanout stems and logic gates, followed by local node simplifications. We guide the retiming of registers across fanout stems to induce equivalence relations among them, which are exploited for subsequent logic simplification. Our technique is able to analyze correlation of logic across register boundaries during simplification. We strive to minimize the increase in number of registers without sacrificing the cycle-time performance. The results demonstrate a favourable performance/ area trade-off when compared with optimally retimed circuits.

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits [p. 643]

M. Papaefthymiou, E. Friedman, X. Liu

This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths are considered, circuits optimized by the combined application of the two techniques are more tolerant to delay variations than when optimized by either of the two techniques separately. A novel mixed-integer linear programming formulation is given for simultaneous retiming and clock scheduling with a target clock period and tolerance under setup and hold constraints. Experiments with LGSynth93 and ISCAS89 benchmark circuits demonstrate the effectiveness of the combined optimization. For half of the test circuits, tolerance to delay variations increased by at least 23% over the separate application of retiming and clock scheduling. Moreover, for two thirds of the test circuits, maximum tolerance improved by at least 11%.

Retiming Sequential Circuits with Multiple Register Classes [p. 650]

K. Eckl, C. Legl

Retiming is an efficient technique for redistributing registers in synchronous circuits in order to improve the circuit performance. However, the traditional retiming approaches cannot handle circuits whose registers are controlled by different clock, reset, and load enable signals. We present basic theory and a comprehensive retiming approach for circuits with multiple clock, reset, and load enable signals. We retime these circuits having multiple register classes without explicitly modeling the reset or the load enable by additional logic. The presented concepts can be combined with a wide range of existing retiming approaches. Experimental results from retiming real designs for clock period minimization show the efficiency of the new approach.

Session 10B: Modelling of Interconnects

In deep submicron design the modelling of interconnect becomes increasingly important. The first paper describes technologies for the modelling and analysis of parasitic coupling effects for large VLSI design. The other two papers present different approaches to modelling and reduction of interconnect networks.

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs [p. 658]

L. Ye, F. Chang, P. Feldmann, R. Chadha, N. Nagaraj, F. Cano

Interconnect parasitics are playing a dominant role in determining chip performance and functionality in deep-submicron designs. This problem is compounded by increasing chip frequencies and design complexity. As parasitic coupling capacitances are a significant portion of total capacitance in deep-submicron designs, verification of both performance and functionality assumes greater importance. This paper describes techniques for the modeling and analysis of parasitic coupling effects for large VLSI designs. Analysis results from a controlled experimental setup are presented to show the need for accurate cell models. Results from application of these techniques on a leading edge Digital Signal Processor (DSP) design are presented. Accuracy comparison with detailed SPICE-level analysis is included.

Coupled Noise Estimation for Distributed RC Interconnect Model [p. 664]

J. Wang, Q. Yu, E. Kuh

With the increase in signal speed and the development of process technology, distributed RC line model is found to be more suitable for on-chip interconnects than lumped RC model, especially for interconnects around and below 0.25um. In this paper, we first describe a new explicit form for crosstalk approximation for coupled RC lines. Then we introduce a novel passive model order reduction technique for distributed RC lines. These two parts serve as two steps in static noise analysis of full on-chip interconnect networks which are called pruning process and static analysis process.

Projective Convolution: RLC Model-Order Reduction using the Impulse Response [p. 669]

B. Sheehan

Projective convolution (PC) is a provably passive and numerically well-conditioned model-order reduction technique for large RLC circuits including those with floating capacitors or inductor loops. Unlike moment-matching which operates in the frequency domain, PC is positioned squarely in the time domain: it matches the impulse response of a circuit by projecting with the Krylov space formed by solving the discretized differential equations of the circuit. PC gives excellent results for coupled lines, large RLC meshes, and clock trees.

Session 10C: Design Reuse Methodologies for Virtual Components and IP

The first paper presents a design space layer that is introduced to support both IP-based design methodologies and traditional design methodologies. The second paper introduces a Java-CAD framework that uses remote components and that supports secure Internet protocol for a smooth transition between component evaluation. The third paper presents a methodology to decrease re-design effort . This methodology is implemented on an already existing reuse management system.

The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs [p. 676]

M. Jacome, H. Peixoto, A. Royo, J. Lopez

A novel library layer, called the "design space layer," is proposed, aimed at supporting both, IP-based and traditional "in-house" design methodologies, during early design space exploration. Strategies for effectively pruning the large design spaces characteristic of system-on-a-chip designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of design objects, and is thus easily scalable. A design space layer developed for encryption applications is presented and discussed in some detail.

Specification and Validation of Distributed IP-based Designs with JavaCAD [p. 684]

M. Dalpasso, A. Bogliolo, L. Benini

This paper presents JavaCAD, a new Java-based CAD framework for the design, validation and simulation of systems using third-party components with reciprocal intellectual property (IP) protection. The designer can use remote components with a dedicated and secure Internet protocol, that guarantees IP protection and supports a smooth transition between component evaluation and purchase.

Object-Oriented Reuse Methodology for VHDL [p. 689]

C. Barna, W. Rosenstiel

In the reuse domain, the necessity of finding a new, more suitable description language opposes the need to make reuse an accepted practice, and thus related to standards. This paper presents a new method to reuse VHDL described components in an IP centric manner. The basic object reuse model uses an object-oriented extension of VHDL, Objective VHDL. In contrast to conventional reuse approaches, which imply a considerable re-design effort, this new approach bridges the gap between design and reuse integration. The methodology is implemented in the form of a Reuse Management System which handles the classification, modification, adaption, storage and retrieval of the reuse components.

Session 10D: Embedded Tutorial -- Multi-language System Design

Contributors: Rolf Ernst, TU Braunschweig, D; Ahmed Amine Jerraya, TIMA, F

Multi-language System Design [p. 696]

A. Jerraya, R. Ernst

Session 10E: RAM BIST

The first two papers address built-in self-test of Random Access Memories. Symmetric transparent BIST is presented as a self-test method that does not destroy the content of the RAM. The second paper presents architectural differences of BIST engines for RAMs. The authors of the third paper discuss self repair of RAMs and the implications on yield.

Symmetric Transparent BIST for RAMs [p. 702]

S. Hellebrand, H. Wunderlich, V. Yarmolik

The paper introduces the new concept of symmetric transparent BIST for RAMs. This concept allows to skip the signature prediction phase of conventional transparent BIST approaches and therefore yields a significant reduction of test time. The hardware cost and the fault coverage of the new scheme remain comparable to that of a traditional transparent BIST scheme. In many cases, experimental studies even show a higher fault coverage obtained in shorter test time.

On Programmable Memory Built-in Self Test Architectures [p. 708]

K. Zarrineh, S. Upadhyaya

The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are presented. The proposed microcode-based memory BIST unit is more efficient and flexible than existing architectures. Test logic overhead of the proposed programmable versus non-programmable memory BIST architectures is evaluated. The proposed programmable memory BIST architectures could be used to test memories in different stages of their fabrication and therefore result in lower overall memory test logic overhead. We show that the proposed microcode-based memory BIST architecture has better extendibility and flexibility while having less test logic overhead than the programmable FSM-based memory BIST architecture.

A Physical Design Tool for Built-In Self-Repairable Static RAMS [p. 714]

K. Chakraborty, A. Gupta, M. Bhattacharya, S. Kulkarni, P. Mazumder

A novel physical design tool, BISRAMGEN, that generates layout geometries of parametrized built-in self-repairable SRAM modules, producing significant improvement in testability, reliability, production yield and manufacturing cost of ASICs and microprocessors with embedded RAMs, is presented.
Key words and phrases: Built-in self-repair (BISR), yield, reliability

Session 11B: Panel -- Java, VHDL-AMS, Ada or C for System Level Specifications?

Java, VHDL-AMS, Ada or C for System Level Specifications? [p. 720]

W. Nebel

This technical panel discussion compares and discusses the suitability of new and established languages for creating executable specifications of heterogeneous embedded systems. The comparison is made by champions of the languages JAVA, VHDL-AMS, ADA and C based on a common example, a portal crane. In particular the panel focuses on issues like modeling efficiency in different domains, execution performance and reusability.

Case Study: System Model of Crane and Embedded Control [p. 721]

E. Moser, W. Nebel

A case study of a crane is defined for the evaluation of system description languages. The plant (car and load) is given as a fourth-order linear system. The embedded control includes sensors, actuators, two control strategies, and diagnosis.

Session 11C: Hot Topic -- IP And Reuse

Virtual Components Application and Customization [p. 726]

J. Agaësse, B. Laurent

The competitive pressure for time-to-market and the tremendous integration capacity provided by the silicon technology developers has raised the promise of systems-on-a-chip. This inescapable evolution however increases the need for cost effective design methodologies and solutions, and the electronic engineering and design community is now firmly convinced that it can not be accomplished without a systematic use of already designed and qualified components, in a similar approach to the one already familiar to software developers. Complex system functions, improperly named IPs, are delivered by ASIC suppliers, created by the customer or developed by independent specialized companies, and offered to system designers, in the form of dedicated predesigned circuit blocks, allowing them to best use their expertise and creativity and finally keep pace with the dramatic productivity challenge required to make the system level silicon a reality.

Design Methodology for IP Providers [p. 728]

J. Haase

Based on their experience in the IP business including a large library of DesignObjects TM (Virtual Components) and lots of design-ins world-wide, SICAN has developed a design methodology for production of Virtual Components. This methodology includes appropriate design-flows for the IP-development as well as prerequisites and methods for successful application in customers' projects. This production flow will be completed by approaches for evaluation.

The session will present different views on the same hot topic : IP and Reuse from the perspective of the IP provider and the IP user. Discussing and presenting each viewpoint, while the topic will be introduced by the state of the art presentation to guide participants into the reuse domain. At the end, a panel discussion is planned to invite the attendees to actively participate in the discussion by asking burning questions to the presentors.

Session 11D: Special Session -- Large European Programs in Microelectronic System and Circuit Design

Large European Programs in Microelectronic System and Circuit Design [p. 734]

P. Dewilde

MEDEA's Contribution to the Strength of European Design and CAD

A. Sauer

Electronic Systems Design in the IST Program

H. Forster

ITEA -- Information Technology and European Advancement

E. Daclin

Session 11E: Sequential Circuit Test Generation

The first paper presents a novel approach to testing sequential circuits by using multi-level decision diagrams. The second paper presents an ATPG system which focuses on discovering the illegal state space. The last contribution introduces a new testing strategy based on a frozen clock strategy which temporarily suspends the sequential behaviour of the circuit.

Sequential Circuit Test Generation using Decision Diagram Models [p. 736]

J. Raik, R. Ubar

A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning and conformity test generation procedures. Structural faults in both, datapath and control part are targeted. High-level simplified and fast symbolic path activation strategy is combined with random local test pattern generation for functional units. Current approach has achieved high fault coverages for known sequential circuit benchmarks in a very short time.

Illegal State Space Identification for Sequential Circuit Test Generation [p. 741]

M. Konijnenburg, J. van der Linden, A. van de Goor

Test generation for (synchronous) sequential circuits (STPG) has a huge search space, which often prevents successful test generation or untestability proof. In this paper four new techniques are proposed to expand the known Global Illegal State (GIS) space, in order to reduce the search space. These techniques use the known GISes to generate candidate GISes, which have to be proven unjustifiable. This is an effective method to improve STPG performance because the number of stored GISes is reduced, saving memory and CPU time, while covering a larger part of the GIS space. To accelerate GIS space identification, we propose the legal state cache, to avoid useless justification repetitions. A data-structure is proposed to reduce the memory usage of the (G)ISes up to 10 times, and to accelerate GIS usage. Experimental results show a significant improvement in fault efficiency and CPU usage.

FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy [p. 747]

Y. Santoso, M. Merten, E. Rudnick, M. Abramovici

Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends the sequential behavior of the circuit by stopping its clock and applying several vectors to increase the number of faults detected without changing the circuit state. Results show that test sets generated using the new approach are more compact than those generated by previous approaches for many circuits.

Posters

Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms [p. 754]

F. Corno, M. Sonza Reorda, G. Squillero

Industrial design flows for electronic circuits typically include at least one optimization step. During this step, the circuit is analyzed and modified in order to improve some specific characteristic, such as speed, size, or power consumption, without modifying its logic behavior. Woefully, exact-by-constructions optimization methods are not always applicable, and designers frequently need to validate the correctness of the optimization process by verifying the equivalence between the optimized design and the original one.

Interval Diagram Techniques for Symbolic Model Checking of Petri Nets [p. 756]

K. Strehl, L. Thiele

Symbolic model checking tries to reduce the state explosion problem by implicit construction of the state space. The major limiting factor is the size of the symbolic representation mostly stored in huge binary decision diagrams. A new approach to symbolic model checking of Petri nets and related models of computation is presented, outperforming the conventional one and avoiding some of its drawbacks. Our approach is based on a novel, efficient form of representation for multi-valued functions called interval decision diagram (IDD) and the corresponding image computation technique using interval mapping diagrams (IMDs). IDDs and IMDs are introduced, their properties are described, and the feasibility of the new approach is shown with some experimental results.

Variable Reordering for Shared Binary Decision Diagrams using Output Probabilities [p. 758]

M. Thornton, J. Williams, R. Drechsler, N. Drechsler

The Shared Binary Decision Diagram (SBDD) with negative edge attributes can represent many functions in a compact form if a proper variable ordering is used. In this work we describe a technique for reordering the variables in an SBDD to reduce the size of the data structure. We use a heuristic to formulate a technique for the reordering problem based on probability metrics.

Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering [p. 760]

C. Meinel, C. Stangier

Model checking has been proven to be a powerful tool in verification of sequential circuits, reactive systems, protocols, etc. The model checking of systems with huge state spaces is possible only if there is a very efficient representation of the model. Ordered Binary Decision Diagrams (OBDDs) allow an efficient symbolic representation of the model.

Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems [p. 762]

W. Fornaciari, D. Sciuto, C. Silvano

This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed model can consider any cache configuration in terms of size, associativity and block. It includes also the most widely adopted power oriented encoding techniques for data and address buses. Experimental results show how the proposed model can be effectively adopted to configure the memory hierarchy and the system bus architecture from the power point of view.

Emulation of a Fast Reactive Embedded System using a Real Time Operating System [p. 764]

K. Weiß, T. Steckstor, W. Rosenstiel

This paper presents the emulation of an embedded system with hard real-time constraints and response times of about 220ms. We show that for such fast reactive systems, the software overhead of a real time operating system becomes a limiting factor. We analyze the influence of novel microcontroller features, e.g., different on-chip caches, which tend to accelerate execution, but make it less predictable. These investigations have been conducted using our own emulation environment called SPYDER-CORE-P1.

The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach [p. 766]

J. Maestro, D. Mozos, R. Hermida

As the Codesign problems become more and more complex, characterizing the scheduling and allocation details of the tasks with macroscopic magnitudes easy to handle, can help to solve them in an efficient way.

Codesign of Embedded Systems based on Java and Reconfigurable Hardware Components [p. 768]

J. Fleischmann, K. Buchenrieder, R. Kress

In the design of embedded hardware/software systems, exploration and synthesis of different design alternatives and co-verification of specific implementations are the most demanding tasks. Networked embedded systems pose a new challenge to existing design methodologies as novel requirements like adaptivity and runtime-reconfigurability arise. In this paper, we introduce a co-design environment based on the Java language which supports specification, co-synthesis and prototype execution for dynamically reconfigurable hardware/software systems.

ADOLT -- An ADaptable On-Line Testing Scheme for VLSI Circuits [p. 770]

A. Maamar, G. Russell

ADOLT permits the error detection capabilities of a CED scheme to be adapted to the error detection requirements of an application. This reduces the impact of the scheme on the design in terms of area overheads and the effect on performance. The scheme uses a slightly modified version of Dong's Code [1] and gives a more efficient implementation than previous methods [2,3].

Integrated Resource Assignment and Scheduling of Task Graphs using Finite Domain Constraints [p. 772]

K. Kuchcinski

This paper presents an approach to modeling of task graphs using finite domain constraints. The synthesis of such models into an architecture consisting of microprocessors, ASICs and communication devices, is then defined as an optimization problem and it is solved using constraint solving techniques. The presented approach offers an elegant and powerful modeling technique for different architecture features as well as heterogeneous constraints. The extensive experimental results prove the feasibility of this approach.

A Method of Distributed Controller Design for RTL Circuits [p. 774]

C. Papachristou, Y. Alzazeri

This paper describes a design or redesign technique to reduce the control path delay and thus improve the performance of an RTL circuit. The basic idea is to replace an existing centralized controller of an RTL circuit with a distributed controller structure which is made up of multiple local controllers. By placing local controllers close to the datapath resources they control reduces the control wire length which in turn increases the circuit performance, especially at higher frequencies where interconnect delays are dominant. The approach begins with a datapath partitioning into distinct functional blocks, local controller extraction algorithm, followed by and hierarchical floor planning. Two local controller styles are presented, the communicating and the and non-communicating local controller, CCL and NCCL, respectively.

OTA Amplifiers Designed on Digital Sea-of-Transistors Array [p. 776]

J. Choi and S. Bampi

This paper presents measurement results of OTA (Operational Transconductance Amplifiers) designed in 1.0 m CMOS Digital technology implemented in two different methodologies: in a fixed-size transistors array and in a full-custom design. Some characteristic parameters of OTA's are compared with HSPICE simulations.

A DAG-Based Design Approach for Reconfigurable VLIW Processors [p. 778]

C. Alippi, W. Fornaciari, L. Pozzi, M. Sami

This paper explores the possibility of enabling a partial customisability of the Instruction Set of Very Long Instruction Wold processors for embedded applications, by exploiting Field Programmable Gate Arrays technology. A formal methodology is presented leading to selection of the application critical parts, whose RFUs (Reconfigurable Functional Units) implementation allows the reduction of overall execution time. Experiments performed on representative benchmarks show the applicability of the proposed approach.

A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis [p. 780]

J. Wu, E. Rudnick, G. Greenstein

A new fault list reduction approach is proposed for use in the first stage of a two-stage bridge fault diagnosis procedure. Modified structural analysis and layout extraction procedures are performed to obtain a reduced realistic bridge fault list that can be used in the second stage, which employs diagnostic fault simulation. The fault list reduction approach can reduce the final candidate bridge fault list by 92% to 99% compared with the diagnosis results achieved by the diagnostic fault simulator alone.

An Object-Based Executable Model for Simulation of Real-Time HW/SW Systems [p. 782]

O. Pasquier, J. Calvez

This paper describes a simulation technique for Real-Time Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions from a high-level functional description to a Hw/Sw partitioned design. The same model, enhanced with algorithms, can be used to simulate interpreted models in order to observe the behavior of a whole system and its environment, as well as uninterpreted models which are useful for performance estimation and so to help Hw/Sw partitioning. Our (co-)simulation technique is based on the translation of a high level model of the application into a C++ program which uses a library of predefined classes. While running, the program produces an event trace which contents can be set by the user. This technique allows to quickly analyze the influence of application or architecture parameters on the application behavior.

An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic Systems [p. 784]

S. Scherber, C. Müller-Schloer

The complexity of mechatronic systems increases continuously. The need of simulation to evaluate these systems in an early design stage is an evident fact. This paper presents a new approach for simulation of heterogeneous mechatronic systems. The aim of the development was to combine openness and flexibility with a high simulation speed and accuracy. Additionally to the description of algorithms and methods, the implementation and an example application are discussed.

Software Bit-Slicing: A Technique for Improving Simulation Performance [p. 786]

P. Maurer, W. Schilp

For some types of simulation, it is difficult or impossible to improve performance by packing several vectors to be packed into a single word. One example of such an algorithm is Inversion Algorithm, which does not represent net values in the conventional way. This paper presents a novel technique, called software bit-slicing, for performing simultaneous simulation of several input vectors on a conventional uniprocessor. As with conventional vector-packing techniques, this technique is able to assign a different input vector to each bit of a word, permitting the simultaneous simulation of n vectors, where n is the number of bits in a word. The Inversion Algorithm is used to give an example of this technique. For this example, a 6x speedup can be realized by using software bit-slicing. The same technique should be widely applicable to many different types of simulation.

Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI [p. 788]

F. Martinolle, C. Dawson, D. Corlette, M. Floyd

Nowadays, designs become more and more complex and are often developed by several teams that may use different Hardware Description Languages. Mixed Verilog/VHDL designs are proliferating because teams choose different languages or because they are importing intellectual property libraries of VHDL or Verilog cells. The authors of paper [1] which compares Verilog and VHDL semantics conclude that there is enough overlap between the two languages for tools vendors to consider building bilingual tools such as compilers, simulators etc ... In this paper we analyze the requirements for a mixed language GUI and explain how the compatibility and interoperability of the standard Verilog and VHDL language procedural interfaces was key to build SimVision, Cadence NCSimulator TM graphical debugging and verification environment. The principles highlighted in this paper can also be applied to other kinds of applications such as Verilog/VHDL co-simulation, testbench generation etc ... In the following, we will focus on the problems inherent to a Verilog/VHDL GUI development.

Experiences with Modeling of Analog and Mixed A/D Systems based on PWL Technique [p. 790]

J. Dabrowksi, A. Pulka

The paper discusses the implementation problems of the PWL macrosimulation technique relevant to functional/RTL level. Principles of the actual PWL approximation algorithm are briefly elaborated with respect to basic building blocks used for synthesis. Based on it the aspects of analog modeling in VHDL environment are considered. Different approaches to modeling of simple blocks and complex structures including some higher order effects are presented. Special attention is paid to feedback loop structures that require iterations. In mixed A/D modeling the signal conversion between PWL and logic domains is emphasized.

A One-Bit Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection [p. 792]

I. Rayane, J. Velasco-Medina, M. Nicolaidis

A new BIST technique for embedded operational amplifiers in mixed-signal circuits is presented in this paper. The technique is based on the detection of the slew-rate deviation, which is a sensitive parameter to defects. The BIST circuitry requires a small area overhead. It is compatible with digital parts since it uses only logic gates, and generates a One-Bit-Signature (OBS), which offers a good observability of the test response. In order to validate the proposed BIST technique, an Op Amp circuit has been considered as test vehicle. Simulation results show that the proposed technique offers a high fault coverage.